Semi-Soft Bit Generation During Corrective Memory Reads
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Solution Overview
Problem
Existing memory devices face inefficiencies in corrective read operations due to cell-to-cell interference and intrinsic charge loss, leading to increased error rates and memory device reliability issues, which are exacerbated by the need for additional read operations to obtain soft bit data, resulting in high latency and reduced performance.
Innovation Solution
Generating semi-soft bit data during corrective read operations by utilizing a local media controller to reserve latches for storing aggressor and hard bit data, and performing exclusive NOR operations on strobe read data to reduce the need for separate soft bit reads, thereby improving read accuracy and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate soft bit read operations are performed to obtain soft bit data, then read accuracy is improved, but latency increases and performance decreases
Solution Approach 1:
The patent merges the acquisition of hard bit data and soft bit data into a single corrective read operation. The media controller generates both types of data simultaneously by performing read operations on target memory cells and adjacent memory cells, then processes them together to produce hard bits and soft bits without requiring separate read operations, thereby reducing latency while maintaining read accuracy
Solution Approach 2:
The patent performs preliminary actions by obtaining cell state information from adjacent memory cells before performing the corrective read operation on target memory cells. This preliminary acquisition of aggressor data allows the system to generate soft bit data during the same operation that retrieves hard bit data, eliminating the need for subsequent separate soft bit reads and reducing overall latency
2Reliability
If additional read operations are performed to handle cell-to-cell interference and charge loss, then error rates are reduced, but performance decreases due to increased operation count
Solution Approach 1:
The patent segments the memory system into target memory cells and adjacent memory cells, treating them differently in the corrective read operation. By identifying and separately processing aggressor cells (adjacent cells with programmed data) and victim cells (target cells being read), the system can apply targeted error correction while maintaining high performance through efficient resource utilization
Solution Approach 2:
The patent introduces cell state information as an intermediary element that mediates between the raw read data and the final corrected data. This intermediary information about adjacent cell states allows the media controller to generate accurate soft bit data that reflects the actual interference conditions, improving error correction reliability without requiring multiple additional read operations
Data Source
AI summary
Systems and methods are disclosed including a memory device comprising a memory array and control logic, operatively coupled with the memory array. The control logic can performing a set of strobe reads on a set of target cells of a plurality of memory cells in the memory array and identify, by performing a lookup of a reference table, at least one strobe read, from the set of strobe reads, for generating semi-soft bit data based on cell state information of a group of adjacent cells. For a target cell of the set of target cells, the semi-soft bit data is generated based on data obtained from the at least one strobe read.