Memory Device Error Correction via Idle Scrubbing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Magnetoresistance elements in magnetic memory devices are prone to unintentional resistance state changes, leading to data errors that existing technologies struggle to reliably correct without compromising performance.
Innovation Solution
A memory device with error correction circuits that perform scrubbing operations during idle times, using syndromes to correct up to N bits of errors during scrubbing and up to M bits (where M < N) during reading, maintaining high-speed performance and improving data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction circuits perform scrubbing operations to correct errors in magnetoresistance elements, then data reliability is improved, but device complexity and processing time increase
Solution Approach 1:
The patent performs scrubbing operations during idle times before actual data access occurs. Error correction circuits proactively detect and correct errors in magnetoresistance elements during periods when the memory device is not being accessed, thereby improving data reliability without impacting normal read/write operations. This preliminary error correction prevents errors from affecting data integrity during subsequent access operations.
2Reliability
If error correction circuits correct up to N bits of errors during scrubbing, then data reliability is improved, but processing speed during reading operations may be reduced
Solution Approach 1:
The patent performs comprehensive error correction during idle times before actual data access. By correcting up to N bits of errors during scrubbing operations that occur during idle periods, the system ensures high data reliability while maintaining fast read speeds during actual data access operations. The heavy error correction processing is done in advance, so when data is actually read, the corrections are already in place.
Solution Approach 2:
The patent implements periodic scrubbing operations during idle times to correct errors in magnetoresistance elements. Error correction is performed periodically when the memory device is idle, rather than continuously or during every read operation. This periodic approach maintains high data reliability while avoiding speed penalties during active data access operations.
3Reliability
If error correction circuits correct up to M bits of errors during reading operations, then data reliability is improved, but processing time increases
Solution Approach 1:
The patent performs error correction during idle times before actual data access operations. By correcting errors in advance during periods when the memory device is not being accessed, the system improves data reliability without adding processing time to actual read operations. The error correction is completed beforehand, so data can be read immediately when access is requested.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses erroneous bits within a desired range, enhancing data reliability during scrubbing while ensuring high-speed performance and quick data transmission during reading operations.
Implementation Method 1
A memory device using a magnetoresistance element is known as a magnetic memory device included in a memory system
Data Source
AI summary
A memory device of one embodiment includes memory elements which store data and parity; a first decoder which, when scrubbing of the data is performed while no external access is being made to the memory device, uses a syndrome generated from the data and the parity to correct an error of a maximum of N bits in a unit of the data; and a second decoder which, when reading of the data is performed, uses the syndrome to correct an error of a maximum of M bits in a unit of the data. The N bits represent the number of bits smaller than the N bits.