eFuse Memory Cell Layout for Stable Programming Current
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Solution Overview
Problem
Conventional eFuse memory cells face issues with large MOS selection transistors due to substrate bias effects, leading to reduced current capacity and increased chip area, and programming currents are affected by voltage drops across bit lines, compromising reliability and layout efficiency.
Innovation Solution
The eFuse memory cell employs two identical NMOS transistors manufactured through a Gate-All-Around (GAA) process, connected in a five-port configuration with shared programming power supply, eliminating substrate bias effects and ensuring consistent programming current across all cells, thereby simplifying circuit design and reducing overall area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MOS selection transistors are used in eFuse memory cells, then the transistor provides basic selection function, but the substrate bias effect reduces current capacity and increases transistor size
Solution Approach 1:
The selection transistor function is segmented into two separate NMOS transistors (first selection transistor and second selection transistor), each handling part of the selection task. This segmentation allows each transistor to be smaller while collectively providing sufficient current capacity, resolving the contradiction between individual transistor size and overall current capability.
Solution Approach 2:
The patent applies different connection configurations to different parts of the circuit: the first selection transistor uses gate connection to bit line while the second uses gate connection to word line. This local differentiation optimizes current flow paths and reduces substrate bias effects in specific regions, improving overall current capacity without increasing total area.
2Reliability
If programming current flows through bit lines to reach memory cells, then current delivery is achieved, but voltage drops in bit lines affect programming reliability
Solution Approach 1:
Instead of flowing current through the bit line from the bit line driver to the memory cell, the patent inverts the current path by connecting the first selection transistor's gate to the bit line, allowing the transistor to be controlled by bit line voltage while current flows through the selected cell from the word line side. This inversion eliminates the voltage drop issue in the bit line.
Solution Approach 2:
The first selection transistor acts as an intermediary between the bit line and the fuse link. By controlling current flow through its gate-terminal connection to the bit line, it mediates the interaction between bit line signals and programming current, preventing direct voltage drops across the bit line while maintaining reliable programming capability.
3Reliability
If different driving circuits are used for row and column memory cells, then specific programming current requirements are met, but circuit complexity and chip area increase
Solution Approach 1:
The patent makes both selection transistors identical in structure and function, with each capable of being controlled by either bit line or word line signals. This universal design allows the same transistor circuit to serve multiple functions in different locations of the memory array, eliminating the need for different driving circuits for rows and columns, thereby reducing overall circuit complexity.
Solution Approach 2:
The patent employs homogeneous transistor designs where both the first and second selection transistors have identical structures, dimensions, and electrical characteristics. This homogeneity simplifies the driving circuit design as uniform transistors require uniform control, reducing the complexity differences between row and column driving circuits while maintaining adequate programming current delivery.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances current flow capacity, improves programming reliability, and reduces chip size by eliminating voltage drops and simplifying layout, while maintaining consistent programming current across all cells.
Implementation Method 1
The eFuse memory cell employs two identical NMOS transistors manufactured through a Gate-All-Around (GAA) process
Implementation Method 2
A MOS transistor manufactured through a conventional process has a substrate bias effect (i.e., a body-effect), which reduces the current capacity of the transistor
Implementation Method 3
eFuse memory realizes a programming function by means of electromigration or fusing when the current flows through a fuse-link
Implementation Method 4
eFuse memory realizes a programming function by means of electromigration or fusing when the current flows through a fuse-link
Data Source
AI summary
The present disclosure discloses an eFuse memory cell, which comprises a first selection transistor, a second selection transistor and a fuse-link, wherein a gate terminal of the first selection transistor is used as a BL port, a drain terminal of the first selection transistor is used as a Q port, and a source terminal of the first selection transistor is connected to a drain terminal of the second selection transistor as a SA port; a gate terminal of the second selection transistor is used as a WL port, and a source terminal of the second selection transistor is connected to one end of the fuse-link; the other end of the fuse-link is used as a gnd port. The present disclosure further discloses an eFuse memory array consisting of the eFuse memory cells.