Floating Wordline Control for Partial NAND Block Reads

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Solution Overview

Problem

Existing memory sub-systems face challenges with higher read bit error rates (RBER) due to partially-programmed blocks, which are not effectively addressed by padding or look-up tables, and adding dedicated voltage regulators is undesirable.

Innovation Solution

Implement floating gate control on unprogrammed wordlines by disconnecting them during the ramp-up of passthrough voltage, combined with adjusted SGS and dummy wordline ramp timing, to manage passthrough voltage levels without additional regulators.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If padding or look-up tables are used to address partially-programmed blocks, then read reliability may be improved, but device complexity and storage requirements increase

Engineering Contradiction:
Improveread bit error rateVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the problematic unprogrammed wordlines from the block and handles them separately through floating gate control during read operations. By isolating these wordlines and applying different voltage levels, the system avoids the need for padding or look-up tables, thereby reducing device complexity while maintaining read reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies local quality by treating programmed and unprogrammed wordlines differently within the same block. Unprogrammed wordlines receive floating gate control with adjusted voltage levels, while programmed wordlines operate normally. This localized differentiation eliminates the need for global workarounds like padding or look-up tables.

Inventive Principle:
Principle #3Local quality

2Reliability

If dedicated voltage regulators are added to manage passthrough voltage levels, then read reliability is improved, but cost and footprint increase

Engineering Contradiction:
Improveread bit error rateVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements self-service by using the existing floating gate structure and control circuits to manage voltage levels during read operations. The system leverages already-present components (control logic, wordline drivers) to provide differentiated voltage control without requiring external dedicated voltage regulators, thereby avoiding additional cost and footprint.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent makes existing control circuits multi-functional by having them serve both normal read operations and the specialized task of managing unprogrammed wordlines. The same control logic that handles programmed wordlines also manages unprogrammed wordlines through floating gate control, eliminating the need for separate dedicated voltage regulators.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260024591A1Floating gate-based partial block handling in a memory sub-system
Publication Date: 2026.01.22 MICRON TECHNOLOGY INC
  • US20260024591A1 patent drawing
  • US20260024591A1 patent drawing
  • US20260024591A1 patent drawing

AI summary

An example system includes: a memory array and a processing device, operatively coupled to the memory array. The processing device is configured to: receive a request to read a subset of memory cells of the memory array; initiate ramping up of a first passthrough voltage to be applied to at least one unselected programmed wordline associated with the subset of memory cells; initiate ramping up of a second passthrough voltage to be applied to at least one unprogrammed wordline associated with the subset of memory cells; cause, during the ramping up of the second passthrough voltage applied to the at least one unselected programmed wordline, the unprogrammed wordline to be electrically disconnected from a voltage source; and cause a read voltage level to be applied to a selected wordline associated with the subset of memory cells.