Flash Memory Erase Method Using Targeted Page Re-erase
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional flash memory devices face challenges in narrowing threshold voltage distributions of erased memory cells due to varying erase speeds and interference from capacitance coupling, which degrades reliability, especially in multi-level cell devices.
Innovation Solution
The method involves performing an erase operation on a page-group basis, with repeated erase verification and additional erase operations only on unerased page groups, using a global control circuit to apply short bursts of erase voltage (20 μs to 1500 μs) and storing unerased page information for targeted re-erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a long erase pulse is applied to ensure all cells are erased, then erase completeness is improved, but threshold voltage distribution widens and reliability degrades
Solution Approach 1:
The erase operation is divided into multiple stages: an initial erase pulse applied to the entire block, followed by verification, and then targeted additional erase pulses only on unerased page groups. This segmentation allows achieving complete erasure while maintaining narrow threshold voltage distribution by avoiding excessive erasure of already-erased cells.
Solution Approach 2:
An initial erase pulse is applied to the entire block before verification to establish a baseline erased state. This preliminary action ensures that most cells are erased, and subsequent targeted operations only address the remaining unerased portions, preventing over-erasure and threshold voltage spread.
2Reliability
If erase operation is performed on the entire block, then all cells are addressed, but erase time increases and capacitance coupling interference occurs
Solution Approach 1:
The block is divided into page groups, and after initial erasure and verification, only the unerased page groups are selected for additional erase operations. This segmentation reduces the number of cells subjected to repeated erase pulses, thereby reducing total erase time and minimizing capacitance coupling interference while ensuring complete erasure of all cells.
3Measurement precision
If repeated erase operations are performed on the entire block, then erase verification accuracy is improved, but device complexity and operation time increase
Solution Approach 1:
Instead of applying erase pulses uniformly across the entire block, the control circuit identifies and targets only the unerased page groups for additional erase operations. This localised approach maintains high verification accuracy by focusing on problem areas while reducing overall operation time and controlling circuit complexity through selective addressing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach narrows threshold voltage distributions, reduces erase operation time, and enhances reliability by ensuring only unerased cells are re-erased, thereby improving the speed and efficiency of the erase process.
Implementation Method 1
the voltages of the drain select line DSL and the source select line SSL are boosted to about 20V due to capacitance coupling with the well
Implementation Method 2
threshold voltage distributions for the memory cells within the memory cell block 11 are moved from positive distributions to negative distributions by means of a high voltage difference between the word lines WL0 to WLi and the well
Data Source
AI summary
A flash memory device and an erase method thereof are included. The erase method includes performing an erase operation of a memory cell block including a plurality of pages, performing an erase verify operation and storing unerased page information about a page including unerased memory cells that have not been normally erased, and performing an additional erase operation of the page including the unerased memory cells based on the unerased page information. When the unerased memory cells exist, the erase verify operation and the additional erase operation are performed repeatedly.