Capacitive Memory Sensing Circuit for Nanoamp Read Signals
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Solution Overview
Problem
Conventional memory devices face challenges in accurately sensing small current signals, such as those in the nanoampere range, during read operations due to the location of sensing circuits being separate from the memory cell array region, leading to performance issues.
Innovation Solution
The sensing circuits are integrated over memory cell pillars within the memory array region, occupying a small footprint, allowing for improved signal sensing and amplification of small signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sensing circuits are located separate from the memory cell array region, then device layout is simplified, but signal sensing accuracy deteriorates for small current signals
Solution Approach 1:
The sensing circuits are integrated within the memory array region by forming them over selected memory cell pillars, merging the sensing function with the storage structure. This integration allows the sensing circuits to be closely coupled with the memory cells, improving signal sensing accuracy for small current signals while maintaining a compact overall device layout.
Solution Approach 2:
The sensing circuits are formed in the vertical dimension over memory cell pillars rather than in a separate planar region. This three-dimensional integration approach utilizes the vertical space above the memory cell array, allowing sensing circuits to be positioned close to the memory cells without increasing the lateral footprint, thus resolving the contradiction between layout simplicity and sensing accuracy.
2Power
If sensing circuits occupy larger area, then signal amplification capability improves, but memory array density deteriorates
Solution Approach 1:
The sensing circuits are nested within the memory array region by positioning them over selected memory cell pillars. This nesting approach allows the sensing circuits to share the same physical space as the memory cells, utilizing vertical stacking rather than lateral expansion. The sensing circuits can provide sufficient signal amplification capability while occupying minimal additional area, thus maintaining high memory array density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the memory device's performance by enabling accurate sensing and amplification of small current signals, improving read operation reliability.
Implementation Method 1
Memory device including capacitive sensing circuit
Data Source
AI summary
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory device. The memory device includes: a first conductive region; tiers of memory cells; memory cell pillars extending through the tiers of memory cells; a second conductive region coupled to the memory cell pillars and located between the first conductive region and the tiers of memory cells; semiconductor structures separated from each other and located between the first and second conductive regions, the semiconductor structures including a semiconductor structure, the semiconductor structure including a first portion, a second portion, and a third portion between the first and second portions; a first conductive contact located between and contacting the first portion of the semiconductor structure and the first conductive region; and a second conductive contact located between and contacting the second portion of the semiconductor structure and the second conductive region.