On-Die Termination Control for Faster NAND Read Timing
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Solution Overview
Problem
Existing storage devices with on-die termination (ODT) circuits require multiple commands for controlling the operations, leading to increased time delays in data communication.
Innovation Solution
A storage device with a storage controller that provides a first read command, an ODT enable command, a selection chip enable (SCE) command, and an ODT disable command to streamline the operation of ODT circuits, reducing the need for multiple commands and enhancing data communication speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple commands are used to control ODT circuits individually, then precise control of each memory device is achieved, but the time required for data communication increases
Solution Approach 1:
The patent combines multiple individual ODT control commands into a single batch command that can control multiple memory devices simultaneously. The storage controller transmits one command to enable or disable ODT circuits across multiple memory devices at once, reducing the total number of commands and communication time while maintaining precise control over each device's ODT state.
Solution Approach 2:
The invention creates a universal command structure that can address and control ODT circuits in multiple memory devices through a single command transmission. This multi-functional command approach allows the storage controller to manage ODT operations across different memory devices without requiring separate dedicated commands for each device, thereby reducing communication overhead.
2Reliability
If individual commands are sent to each memory device for ODT control, then precise timing control is achieved, but the operational speed of the storage device decreases
Solution Approach 1:
The patent merges multiple individual ODT control operations into a single batch command transmission. The storage controller sends one command that simultaneously controls ODT circuits in multiple memory devices, maintaining precise timing control for each device while significantly improving operational speed by eliminating sequential command transmissions.
3Reliability
If multiple commands are transmitted for ODT control operations, then complete control coverage is achieved, but the complexity of command processing increases
Solution Approach 1:
The patent combines multiple ODT control commands into a single batch command structure. The storage controller processes one unified command that covers all memory devices requiring ODT control, reducing command processing complexity while ensuring complete control coverage through the batch operation mechanism.
Solution Approach 2:
The batch command structure is segmented to include individual control fields for each memory device, allowing the controller to manage multiple devices through a single command while maintaining the ability to address each device specifically. This segmentation approach simplifies the overall command structure compared to transmitting separate commands for each device.
Data Source
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AI summary
A storage device (1000) may include a plurality of non-volatile memory devices (1110, 1120, 1210, 1220) including an on-die termination (ODT) circuit (160, 160a, 160b, 160c), respectively, and a storage controller (1300) configured to provide a first read command to a first non-volatile memory device (1110) among the plurality of non-volatile memory devices (1110, 1120, 1210, 1220), provide an ODT enable command to the plurality of non-volatile memory devices (1110, 1120, 1210, 1220), enable the ODT circuits (160, 160a, 160b, 160c) of the plurality of non-volatile memory devices (1110, 1120, 1210, 1220) in response to the ODT enable command, provide a first selection chip enable (SCE) command to the first non-volatile memory device (1110), and in response to the first SCE command (SCE1), disable a first ODT circuit (160) included in the first non-volatile memory device (1110) among the ODT circuits (160, 160a, 160b, 160c)of the plurality of non-volatile memory devices (1110, 1120, 1210, 1220), and output data stored in the first non-volatile memory device.