Memory Wear Leveling Using Open Bit Counts in SLC Mode
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Solution Overview
Problem
Traditional wear leveling methods for rewritable non-volatile memory modules are ineffective in extending their service life, as they rely on program/erase count or error bits, which fail to address the severe wear caused by tunneling oxide degradation during AI training, especially in SLC mode.
Innovation Solution
A staged wear leveling method that considers the open bit count of physical erasing units, performing a first wear leveling operation when the average program/erase count exceeds a threshold, using open bit count to indicate wear and avoid severe wear by redistributing data to less worn units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional wear leveling methods based on program/erase count are used, then the wear distribution is balanced, but the service life is not effectively extended due to tunneling oxide degradation
Solution Approach 1:
The patent changes the parameter basis for wear leveling from program/erase count to open bit count. By monitoring the number of open bits (bits that have failed to program correctly) in each physical erasing unit, the system identifies units experiencing severe tunneling oxide degradation and redistributes data to healthier units, thereby extending service life
Solution Approach 2:
The patent implements a feedback mechanism by continuously monitoring open bit counts in physical erasing units. This real-time feedback allows the wear leveling algorithm to dynamically adjust data distribution based on actual wear conditions, preventing further degradation in already-worn units
2Reliability
If wear leveling based on error bits is used, then wear condition can be monitored, but it is ineffective in SLC mode with low program/erase count where no error bits are generated
Solution Approach 1:
The patent changes the monitoring parameter from error bits to open bits. Open bits are detected by attempting to program data and checking if the programming succeeded, regardless of whether an error was previously recorded. This parameter change makes the wear leveling method effective in SLC mode with low program/erase count where traditional error bit methods fail
3Productivity
If high program/erase count operations are performed, then data access speed is improved, but tunneling oxide degradation accelerates and wear increases rapidly
Solution Approach 1:
The patent applies local quality by identifying specific physical erasing units with high open bit counts (severe local degradation) and redistributing data from these units to units with lower open bit counts. This localized approach allows high program/erase count operations to continue in healthier units while protecting severely degraded units
Solution Approach 2:
The patent performs preliminary wear assessment by monitoring open bit counts before severe degradation occurs. By detecting units with increasing open bit counts early, the system can proactively redistribute data to prevent catastrophic failure, allowing sustained high-speed operations
Data Source
AI summary
A wear leveling method, a memory storage device and a memory control circuit unit are provided. The wear leveling method includes: obtaining an open bit count of each physical erasing unit; determining whether there is a first physical erasing unit with the open bit count greater than a first threshold; and in response to there being the first physical erasing unit with the open bit count greater than the first threshold, performing a first wear leveling operation on the first physical erasing unit.