Split-Gate Memory Cell Strain Structure for Lower Program-Erase Power
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Solution Overview
Problem
Existing non-volatile memory cells, particularly split-gate non-volatile memories, face high power consumption during programming and erasing operations due to the use of hot carriers, which is inefficient in terms of energy usage and requires complex adjustments for varying memory densities.
Innovation Solution
Increasing the mobility of carriers in the semiconductor channel of the select transistor by incorporating a tensile-strained silicon layer between the gate oxide region and a silicon germanium alloy region, which enhances the number of hot carriers created, thereby reducing power consumption and programming/erasing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If hot carrier injection is used to program or erase the memory cell, then power consumption is reduced compared to Fowler-Nordheim effect, but the number of hot carriers created is insufficient leading to higher actual power consumption and longer programming/erasing time
Solution Approach 1:
The patent changes the physical state of the silicon channel by introducing tensile strain through a silicon germanium alloy layer. This parameter change (from unstrained to tensile-strained silicon) increases carrier mobility and hot carrier generation, resolving the contradiction between power consumption and programming speed by enhancing the efficiency of hot carrier injection.
Solution Approach 2:
The patent uses a composite structure combining silicon and silicon germanium alloy layers. The silicon germanium alloy layer with specific lattice constant creates tensile strain on the adjacent silicon channel layer, improving carrier mobility and hot carrier generation efficiency, thus simultaneously reducing power consumption and programming time.
2Use of energy by moving object
If voltage values are reduced to further decrease power consumption, then energy efficiency improves, but programming/erasing time increases and performance degrades
Solution Approach 1:
By changing the strain state parameter of the silicon channel from unstrained to tensile-strained, the patent increases carrier mobility and hot carrier generation rate. This allows maintaining fast programming/erasing speeds without requiring high voltage, thus reducing power consumption without sacrificing speed.
3Quantity of substance
If memory device density is increased, then storage capacity improves, but electrical conditions must be adjusted for each device making manufacturing and operation more complex
Solution Approach 1:
The patent introduces tensile strain as a physical parameter modification that fundamentally improves carrier mobility and hot carrier generation. This parameter change creates a more robust and efficient memory cell structure that maintains consistent performance across different device densities, reducing the need for complex electrical condition adjustments when scaling memory capacity.
Data Source
AI summary
A non-volatile memory device includes a memory cell having a split gate state transistor and a vertical type select transistor buried in a semiconductor substrate. The memory device includes structure designed to increase the mobility of the carriers in a semiconductor channel of the vertical type select transistor during a programming or erasing operation of the memory cell by hot carriers.