Double-Pulse Write for Phase Change Memory Speed
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Solution Overview
Problem
Phase change random access memory (PRAM) write operations are slower and asymmetric, particularly with the SET phase being slower than the RESET phase, limiting its performance in binary logic applications.
Innovation Solution
A two-step write process is implemented, involving a first pulse with a large amplitude and short duration to re-melt and quench the phase change material, followed by a second pulse with low energy to achieve the SET state, and a verification pulse to ensure accuracy, using a double-pulse process to enhance write speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single write pulse is used for phase change memory, then the write operation is simpler, but the write speed is slower and the SET phase is significantly slower than the RESET phase
Solution Approach 1:
The write operation is segmented into two distinct pulses: a first write pulse to reach an intermediate resistance state, and a second write pulse to reach the final SET state. This segmentation allows each pulse to be optimized independently, improving overall write speed while managing complexity through structured division of the write process.
Solution Approach 2:
The write operation uses periodic pulsed action with specific timing characteristics. The first write pulse has a first duration to reach an intermediate state, followed by a second write pulse with a second duration to complete the transition. This periodic structure enables controlled phase changes at different stages of the write process.
2Speed
If high energy is used to achieve fast write speed, then the write speed improves, but the energy consumption and power increase
Solution Approach 1:
The first write pulse performs preliminary action by transitioning the phase change material to an intermediate resistance state before the second write pulse completes the transition to the final SET state. This preliminary action reduces the energy required for the final transition, optimizing the balance between write speed and energy consumption.
Solution Approach 2:
The write operation changes parameters between pulses: the first write pulse uses specific amplitude and duration to reach an intermediate state, then the second write pulse uses different amplitude and duration parameters to complete the transition. This parameter optimization minimizes energy consumption while maintaining fast write speeds.
3Speed
If the write operation is optimized for speed, then the write speed improves, but the stability and reliability of the SET and RESET states may be compromised
Solution Approach 1:
The write operation includes a verification read operation after applying the write pulses to confirm that the phase change material has successfully transitioned to the desired SET state. This feedback mechanism ensures reliability by verifying the write operation completed successfully, maintaining state stability while achieving fast write speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves the write speed and efficiency of PRAM by reducing write energy and power while maintaining stability of the SET and RESET states, allowing for faster and more reliable data storage.
Implementation Method 1
a first write pulse to a memory cell to a first intermediate state, in which the phase change material is in a middle of a transition from a crystalline state to an amorphous state
Implementation Method 2
the phase change material is in a middle of a transition from a crystalline state to an amorphous state
Implementation Method 3
a second write pulse to the memory cell to a SET state, in which the phase change material is fully transitioned to the amorphous state
Implementation Method 4
a verification read operation is performed to verify that the write operation was successful
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
The present invention discloses a method including: writing a phase change material from a high RESET state to a weakened RESET state with a first step; writing the phase change material from the weakened RESET state to a SET state with a second step, the second step having a lower current than the first step; verifying a parameter of the phase change material wherein if the parameter is higher than a target for a SET state, then repeating the writing with the first step, the writing with the second step, and the verifying until the parameter is lower than the target wherein a current for the first step is decreased by a decrement with each iteration without becoming lower than a current for the second step.