Sense Voltage Adjustment for Multi-Erase Block Memory Arrays

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Solution Overview

Problem

In memory systems with multiple erase blocks coupled to the same string, existing approaches face challenges in accurately sensing the state of memory cells due to 'back pattern' effects, where the conductivity of shared channels changes as programming progresses, leading to data loss and increased bit error rates.

Innovation Solution

The solution involves determining appropriate sense voltage adjustments based on the program state of multiple erase blocks, using an external controller to track and provide program state information for each erase block, allowing for offset calculations to ensure accurate sensing operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple erase blocks are coupled to the same string to increase storage capacity, then storage density is improved, but sensing accuracy deteriorates due to back pattern effects

Engineering Contradiction:
Improvestorage capacityVSAvoidsensing accuracy
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The patent applies parameter changes by adjusting the sense voltage based on the program state of multiple erase blocks. The sense voltage is dynamically modified according to the number of programmed erase blocks to compensate for back pattern effects, thereby maintaining sensing accuracy while utilizing multiple erase blocks for increased storage capacity

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements feedback by tracking the program state of each erase block and using this information to adjust the sense voltage for subsequent sensing operations. The system continuously monitors erase block states and modifies sensing parameters accordingly to mitigate the cumulative back pattern effects across multiple erase blocks

Inventive Principle:
Principle #23Feedback

2Measurement precision

If sense voltage is adjusted based on program state information to mitigate back pattern effects, then sensing accuracy is improved, but device complexity increases due to tracking and calculation requirements

Engineering Contradiction:
Improvesensing accuracyVSAvoidcontrol complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by having the external controller track and store program state information for each erase block in advance. This pre-tracking of erase block states allows the sense voltage to be quickly determined and adjusted without complex real-time calculations during sensing operations, thereby reducing operational complexity while maintaining sensing accuracy

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250006275A1Sense voltage adjustment among multiple erase blocks
Publication Date: 2025.01.02 MICRON TECHNOLOGY INC
  • US20250006275A1 patent drawing
  • US20250006275A1 patent drawing
  • US20250006275A1 patent drawing

AI summary

An apparatus can comprise a memory array comprising multiple erase blocks coupled to a same plurality of strings of memory cells. Control circuitry can be configured to: receive a command corresponding to a sensing operation to be performed on a selected access line of a first group of access lines corresponding to a first erase block; and determine an adjusted sense voltage to be applied to the selected access line in association with performing the sensing operation. The adjusted sense voltage is based on: a quantity of the first group of access lines that are programmed; or a quantity of the second group of access lines that are programmed; or both.