Non-Volatile Memory Atomic Flag for Tearing-Resistant Updates

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Solution Overview

Problem

Existing memory systems face challenges in detecting and resolving tearing events, particularly in non-monotonic programming environments, leading to data corruption and system instability during power interruptions.

Innovation Solution

Implementing a system-level atomic flag using two memory cells to represent a flag value, where the flag is set and cleared sequentially to ensure robustness against tearing events, even in non-monotonic programming environments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single memory cell is used to store a flag value, then the device complexity is reduced, but the reliability deteriorates due to tearing events during power interruptions

Engineering Contradiction:
Improveflag value consistencyVSAvoidmemory cell quantity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The flag storage function is segmented across two memory cells (first and second memory cells) instead of using a single cell. This segmentation allows the system to detect tearing events by comparing the states of both cells and ensures that at least one cell maintains a valid flag value even during power interruptions, thereby improving reliability without excessive complexity increase.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If monotonic programming behavior is assumed, then the device complexity is reduced, but the adaptability deteriorates when dealing with non-monotonic memory systems

Engineering Contradiction:
Improvecompatibility with non-monotonic memoryVSAvoidtearing detection mechanism
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system performs preliminary actions by sequentially programming the first memory cell and then the second memory cell before considering the flag update complete. This preliminary sequential programming approach allows the system to detect tearing events that occur during the programming process and ensures compatibility with non-monotonic memory systems without requiring complex real-time monitoring mechanisms.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback by reading back the values from both memory cells after programming and verifying that they represent a consistent flag state. If a tearing event is detected (inconsistent state), the system can trigger corrective actions such as re-programming, ensuring adaptability to non-monotonic memory behavior through a relatively simple feedback loop.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The atomic flag approach enhances the reliability of memory updates and system operations by minimizing the risk of inconsistent flag values during power interruptions, ensuring accurate data integrity and system stability.

Implementation Method 1

programming the first memory cell to a first voltage value that exceeds a first threshold voltage of the first memory cell

Methodology Applied
Scientific EffectVoltage thresholding:

Implementation Method 2

programming the second memory cell to a second voltage value that is less than a second threshold voltage of the second memory cell

Methodology Applied
Scientific EffectVoltage thresholding:

Data Source

PatentEP4266311B1Non-volative memory system configured to mitigate errors in read and write operations
Publication Date: 2026.01.28 NXP BV
  • EP4266311B1 patent drawingFigure 1
  • EP4266311B1 patent drawingFigure 2
  • EP4266311B1 patent drawingFigure 3

AI summary

A system and method for a memory system are provided. A memory device includes an array of non-volatile memory cells. A memory controller is connected to the array of non-volatile memory cells. The memory controller is configured to perform the steps of receiving a request to read a value of a memory flag, wherein the memory flag includes a 2-bit value stored in a first memory cell and a second memory cell of the array of non-volatile memory cells, reading a first value of the first memory cell, reading a second value of the second memory cell, and determining the value of the memory flag based on the first value and the second value. In embodiments, the memory flag may have more than 2-bits.