3D Semiconductor Memory Device Dummy Hole Surface Patterns
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Solution Overview
Problem
The integration and design flexibility of 2-dimensional semiconductor memory devices are limited due to the high cost and complexity of miniaturization, necessitating the development of 3-dimensional semiconductor memory devices with improved reliability and design freedom.
Innovation Solution
A 3-dimensional semiconductor memory device is designed with a substrate featuring a cell array region and connecting region, including stacked insulation layers and electrodes, vertical structures in channel holes, and dummy structures in dummy holes, with varying surface patterns and diameters to enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If 2-dimensional planar semiconductor device structure is used, then fabrication process is simpler, but integration degree is limited
Solution Approach 1:
The patent transitions from a 2-dimensional planar structure to a 3-dimensional stacked structure by vertically stacking multiple memory cell layers. This dimensional change allows memory cells to be arranged in three dimensions rather than just on a flat plane, significantly increasing the integration degree while maintaining a fabrication process that builds upon existing 2-D manufacturing capabilities through sequential layer formation.
2Area of stationary object
If pattern miniaturization is pursued to increase integration, then area per memory cell is reduced, but fabrication cost and difficulty increase significantly
Solution Approach 1:
Instead of reducing the area of individual memory cells through aggressive pattern miniaturization, the patent increases integration by stacking multiple memory cell layers vertically. This approach maintains larger, easier-to-fabricate cell areas while achieving higher integration through the third dimension, thereby avoiding the exponential cost increases associated with extreme miniaturization.
Solution Approach 2:
The memory device is divided into multiple discrete memory cell layers stacked vertically, with each layer containing complete memory cell structures. This segmentation allows each layer to be fabricated using standard processes while the overall integration is achieved through the stacking of multiple such segments, reducing the need for ultra-fine patterning in any single layer.
3Quantity of substance
If 3-dimensional stacked structure is implemented, then integration degree is improved, but design freedom is constrained by fabrication reliability requirements
Solution Approach 1:
The stacked structure is divided into multiple independent memory cell layers, each containing complete memory cell structures that can be designed and fabricated using established processes. This segmentation provides design freedom within each layer while achieving high integration through vertical stacking, as each layer can be optimized independently without compromising overall fabrication reliability.
Solution Approach 2:
The patent forms complete memory cell structures in each layer before stacking, including all necessary components such as word lines, bit lines, and charge storage elements. This preliminary formation of complete functional units in each layer allows for greater design flexibility and easier integration, as each stacked layer is a self-contained memory cell structure that can be designed independently.
Data Source
AI summary
A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connecting region; a stacked structure including a lower stacked structure and an upper stacked structure sequentially stacked on a substrate, wherein the stacked structure includes an insulating layer and electrodes alternately stacked vertically on the substrate; a vertical structure in a channel hole passing through the lower stacked structure and the upper stacked structure on the cell array region; and a dummy structure in a dummy hole passing through at least one of a lower stacked structure and an upper stacked structure on a connecting region. The connecting region includes a second connecting region on one side of the cell array region and a first connecting region on one side of the second connecting region. A surface pattern shape of the dummy hole in the second connecting region is different from a shape of the dummy hole in the first connecting region.