3D Memory Array Dummy Regions Tapered Sidewalls
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Solution Overview
Problem
The existing semiconductor memory technologies face challenges in achieving uniformity and reducing device defects in 3D memory arrays due to variations in channel region characteristics, leading to unreliable threshold voltages and increased defects.
Innovation Solution
The implementation of a 3D memory array with vertically stacked memory cells, featuring ferroelectric gate dielectric layers and oxide semiconductor channel regions, where dummy memory layers are formed in the top and bottom layers with tapered sidewalls to reduce non-uniformity and improve device performance, while functional memory devices are formed in the middle regions with conductive contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked memory cells are implemented in 3D memory arrays, then device density is improved, but variations in channel region characteristics increase leading to non-uniformity and device defects
Solution Approach 1:
The patent segments the memory array into distinct regions: central regions with functional memory devices and edge regions with dummy memory devices. This segmentation isolates the problematic edge effects that cause non-uniformity in channel region characteristics, allowing the central functional regions to maintain consistent characteristics while still achieving high device density through vertical stacking.
Solution Approach 2:
The patent extracts or removes the problematic edge regions containing dummy memory devices from the functional memory array. By placing dummy devices only in edge regions and excluding them from functional operations, the patent eliminates the source of non-uniformity while preserving the high-density vertical stacking architecture in the central functional regions.
2Quantity of substance
If vertically stacked memory cells are implemented in 3D memory arrays, then device density is improved, but device defects increase due to non-uniform channel region characteristics
Solution Approach 1:
The patent divides the memory array into functional central regions and non-functional edge regions. This segmentation ensures that devices experiencing non-uniform channel characteristics in the edge regions do not compromise the reliability of the functional memory devices in the central regions, thereby maintaining high device density without proportionally increasing defects.
Solution Approach 2:
The patent extracts problematic dummy devices from the functional array and places them only in edge regions. This removal of defective devices from the functional memory space reduces overall device defects while preserving the high-density vertical stacking architecture in the central functional regions.
3Manufacturing precision
If dummy memory layers are formed in top and bottom layers with tapered sidewalls, then non-uniformity is reduced, but device complexity increases
Solution Approach 1:
The patent applies different structural qualities to different regions: dummy memory devices with tapered sidewalls are placed only in edge regions where they serve to uniformize the overall array characteristics, while functional memory devices in central regions maintain their standard structure. This local application of quality improvements reduces overall non-uniformity without unnecessarily complicating the functional devices.
Solution Approach 2:
The dummy memory devices with complex tapered structures serve as sacrificial or non-functional elements that improve overall uniformity but are not intended for functional use. By making these complex structures non-functional (dummy), the patent can afford their structural complexity without compromising the functionality or performance of the actual memory devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device density, reduces device defects, and improves performance by maintaining consistent device characteristics across the memory array, thereby increasing the reliability and efficiency of memory operations.
Implementation Method 1
Each memory cell includes a transistor having a gate dielectric layer and a channel region formed in a recess having sidewalls
Implementation Method 2
Upper and lower regions of the recesses may have tapered sidewalls with widths which narrow in a direction toward a substrate
Data Source
AI summary
3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.