Digital Storage TRIZ Cases
- Redundant Memory Data Correction for Radiation Hardening
A redundant memory system uses error detection circuits to identify data mismatches across multiple storage devices and generate correction signals.
- Semiconductor Memory Input Circuit Frequency Control for Testing Efficiency
Frequency control units generate higher frequency signals from low frequency inputs, allowing simultaneous testing of multiple semiconductor memory devices.
- Dual-Gate Transistor STT-MRAM Read-Write Path Segmentation
A dual-gate transistor separates read and write paths in an STT-MRAM cell to enable independent current control.
- Dynamic Output Delay Selection in Memory Control Devices
A memory control device dynamically selects output delays by combining de-skew and write-levelization components for each rank.
- Soft Error Detection in Memory Latches Using Flip-Flop Comparators
Master and slave flip-flops compare latch outputs to detect soft errors, reducing design complexity and chip area.
- MRAM Free Layer With Doped Metal Insertion Layers
Doped metal insertion layers in the free structure prevent oxygen diffusion while enhancing magnetic exchange coupling for better heat endurance.
- Resistive Memory Programming for Thermal Stress Retention
Pre-programming resistive memory cells restores data states after thermal stress, ensuring reliable retention during assembly.
- Digitally-Controllable Delay for MRAM Sense Amplifier Read Timing
A digitally-controllable amplifier adjusts the enable signal timing for magnetic random access memory sense amplifiers.
- Non-Volatile Memory Write Timing Control Circuit
Write timing control circuit monitors resistance state switching to disable the timing line immediately after write completion, reducing power consumption.
- Core Voltage Generator Dual Discharge Drivers
Dual discharge drivers segment the voltage reduction process to resolve excessive core voltage rise during bit line overdriving operations.
- MRAM Tunnel Barrier Thickness Control for Signal Accuracy
Adjusting the tunnel barrier layer thickness balances electron tunneling efficiency with manufacturing precision for accurate digital signal representation.
- Resistive Memory Measurement System for Data Writing Reliability
A resistive memory measurement system adjusts write voltage to control variable resistor states.
- Semiconductor Memory Device Sub Word Line Voltage Control
Segmented voltage application on the sub word line prevents cell current overshoot and read disturbances while maintaining global bit line charging speed.
- SRAM Margin Recovery via Hafnium Oxide Electron Traps
Hafnium oxide electron traps shift voltage thresholds to rebalance SRAM cells, correcting negative margins caused by bias temperature instability.
- Dual Rail Memory Architecture Level Shifting Optimization
A dual rail memory architecture relocates voltage level shifting to the sense amplifying stage within the VDD power domain.
- Row Decoder and Word Line Driver Voltage Management
Separate power supply voltages in a row decoder and word line driver eliminate CHC protection transistors, reducing GIDL currents and enhancing switching speed.
- Memory Interface Timing Adjustment Circuit for Phase Noise
A memory interface timing adjustment circuit uses a gate leveling mechanism to synchronize data strobe and gate signals.
- CAM Learn Throughput Optimization via Key Cache
A key cache prevents duplicate content-addressable memory entries by storing lookup keys, maintaining high learn rates without throttling router performance.
- Semiconductor Memory Input Output Multiplexing for Terminal Reduction
Multiplexed input output lines recognize commands through control signals, reducing external connection terminals and simplifying printed circuit board layout.
- I/O Line Sense Amplifier Voltage Segmentation
Voltage segmentation in a two-stage I/O line sense amplifier reduces operating current by sixty percent while maintaining column address access speed.
- Bit Line Pre-Charge Timing Control for Flash Memory Peak Current Reduction
Dynamic pre-charge timing control reduces peak current during program operations by adjusting target voltages and ramp rates based on inhibit bit line counts.
- 3D Memory Array Dummy Regions Tapered Sidewalls
Tapered dummy word lines in ferroelectric 3D memory arrays isolate edge defects, maintaining uniform channel characteristics across functional cells.
- Memory Apparatus Dynamic Address Access Time Control
A memory apparatus uses a mimic redundant device comparator to dynamically adjust address accessing time based on measured signal delays.
- Multi-stage Content Addressable Memory Power Optimization
Segmented match lines with distinct pre-charge voltages lower peak currents while preserving search speed in parallel architectures.
- Split Local Data Bus for DRAM Bandwidth
Segmenting the local data bus doubles prefetch width without adding tracks, resolving complexity constraints.
- Semiconductor Target Address Storage Circuit for Refresh Operations
Target address storage circuit counts block selections to generate row addresses, preventing data loss from coupling interference in integrated devices.
- Memory Control Circuit Alternating Refresh Cycles
A memory control circuit alternates data refreshing between two independent cell arrays to maintain system operation.
- Buffered Memory Device Signal Integrity Multi-Drop Bus
Directional drivers in a buffered memory module detect low DQS states to switch driving directions, resolving signal integrity issues on multi-drop buses.
- Semiconductor Data Alignment Circuit for Multi-Mode Operation
Alignment data generation circuit synchronizes latch data with internal strobe signals to produce consistent write data windows.
- Variable Resistive Memory Read Circuit Noise Decoupling
Decoupling units filter clamping and precharge signals to remove noise interference, increasing sensing margin for accurate state differentiation.