Soft Error Detection in Memory Latches Using Flip-Flop Comparators
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in accurately detecting soft errors caused by radiation, particularly in latches and memory cells, due to their temporary and event-specific nature, which can lead to faulty operations in critical applications, and current solutions like ROM arrays and differential voltage/current sensing circuits increase design complexity and chip area without fully addressing errors in control latches.
Innovation Solution
The implementation of a system using master and slave flip-flops in conjunction with a comparator to detect soft errors during memory read/write operations, eliminating the need for additional sensing and timing circuits and ROM arrays, thereby simplifying the design and reducing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ROM array and differential voltage/current sensing circuits are used to detect soft errors, then soft error detection capability is improved, but device complexity and chip area increase
Solution Approach 1:
The patent extracts the error detection function from complex ROM arrays and differential sensing circuits, and implements it using simple flip-flops and XOR gates. The detection logic is separated into individual stage flip-flops that can be integrated into the existing latch structure without requiring additional complex sensing infrastructure.
Solution Approach 2:
The patent creates copies of the latch structure with additional flip-flops and XOR gates that replicate the detection function. Each latch stage gets a corresponding flip-flop copy that captures and compares the latch output, enabling error detection without adding fundamentally new complex circuitry.
2Reliability
If ROM array and differential voltage/current sensing circuits are used to detect soft errors, then soft error detection capability is improved, but chip area increases
Solution Approach 1:
The patent removes the need for large ROM arrays and differential sensing circuits by extracting the essential detection function and implementing it with compact flip-flops and XOR gates. This extraction reduces the chip area significantly while maintaining error detection capability.
Solution Approach 2:
The patent replaces expensive, area-consuming ROM arrays and differential sensing circuits with inexpensive, compact flip-flop and XOR gate structures. These simpler components achieve the same detection function with minimal area overhead.
3Reliability
If ECC is used to correct errors in address and control values, then error correction capability is improved, but errors occurring after latching cannot be detected
Solution Approach 1:
The patent applies preliminary error detection action by capturing the latch output in flip-flops immediately after latching occurs. This preliminary capture enables detection of errors that happen during or after the latching operation, extending the detection window beyond what ECC alone can provide.
Solution Approach 2:
The patent implements feedback by continuously monitoring the latch output through flip-flops and XOR gates. The detected errors are fed back to indicate when corruption has occurred, providing ongoing verification that complements the one-time ECC correction capability.
Data Source
AI summary
A system for detecting soft errors in a memory device includes a latch, a master flip-flop and a slave flip-flop. The latch receives input data (control and/or address signals) at the beginning of a memory operation in response to a rising edge of a first clock signal. The output of the latch is provided to the master flip-flop. The master flip-flop continuously receives and stores the latch output during the memory operation based on a second clock signal. The slave flip-flop receives and stores the output of the master flip-flop at the end of the memory operation based on the second clock signal. A comparator compares the input data with the output of the slave flip-flop to detect soft errors that occur during the memory operation.