Core Voltage Generator Dual Discharge Drivers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor memory devices, the core voltage level often rises excessively due to overdriving operations, making it difficult to recover to the target core voltage level, leading to instability and inefficiency in transistor leakage current and voltage regulation.
Innovation Solution
A core voltage generator with a first and second discharge driver is implemented, activated by specific enable signals for predetermined periods, to efficiently lower the core voltage to the target level, using comparators and NMOS/PMOS transistors to manage discharging rates based on voltage thresholds and reference levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an external power supply voltage is applied to the pull-up power line during overdriving operation, then sensing efficiency is improved, but the core voltage level rises excessively making it difficult to recover to target level
Solution Approach 1:
The discharge operation is segmented into two distinct phases: a first discharge phase using a first discharge driver for initial voltage reduction, and a second discharge phase using a second discharge driver for precise voltage adjustment. This segmentation allows each phase to address specific voltage reduction needs, enabling effective recovery to target level while maintaining sensing efficiency benefits.
Solution Approach 2:
The discharge driver circuit dynamically switches between different discharge modes based on voltage conditions. The first discharge driver operates with higher discharge current for rapid voltage reduction when core voltage rises excessively, while the second discharge driver provides finer control for precise voltage adjustment. This dynamic adaptation resolves the contradiction between rapid voltage recovery and precise level control.
2Manufacturing precision
If the core voltage is discharged through a discharge transistor, then voltage level is reduced, but the discharge rate is extremely slow reducing recovery speed
Solution Approach 1:
The discharge process is divided into two stages with different discharge drivers having different discharge characteristics. The first discharge driver provides rapid discharge for most of the voltage reduction, while the second discharge driver provides precise control for the final adjustment. This segmentation resolves the contradiction between fast discharge rate and precise voltage control.
Solution Approach 2:
The invention changes the discharge current parameter dynamically by switching between two discharge drivers with different current capabilities. The first discharge driver uses higher current for fast discharge, while the second uses lower current for precise control. This parameter change allows the system to achieve both fast discharge rate and precise voltage level control.
3Device complexity
If a single discharge driver is used, then circuit complexity is reduced, but the ability to handle different discharge stages is insufficient
Solution Approach 1:
The discharge driver is segmented into two functional units: a first discharge driver for rapid voltage reduction and a second discharge driver for precise voltage adjustment. Each unit is activated by specific enable signals at appropriate times. This segmentation provides versatile discharge control capability while keeping each individual driver relatively simple.
Solution Approach 2:
The two discharge drivers are activated periodically in sequence based on voltage conditions. The first discharge driver operates during the initial discharge phase, and the second discharge driver activates when finer control is needed. This periodic activation pattern provides adaptable discharge control without requiring both drivers to be always active, managing circuit complexity.
Data Source
AI summary
Provided are a core voltage generator and a method for generating a core voltage in a semiconductor memory device. The core voltage generator includes a first discharge driver for discharging a core voltage terminal for an interval at which the voltage is higher than a target level, in response to a first enable signal activated for a first predetermined period after overdriving a bit line, and a second discharge driver for discharging the core voltage terminal for an interval at which the voltage at the core voltage terminal is higher than the target level by a predetermined threshold, in response to a second enable signal activated for a second predetermined period after overdriving the bit line, wherein the second predetermined period is shorter than the first predetermined period.