Digitally-Controllable Delay for MRAM Sense Amplifier Read Timing
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Solution Overview
Problem
There is a delay between initiating a read operation in magnetic random access memory (MRAM) devices and when the data can be accurately read by digital sense amplifiers, leading to potential errors if the comparison is too soon, and performance issues if the delay is too long.
Innovation Solution
A circuit with a digitally-controllable delay is introduced, using a sense amplifier and a tracking circuit with a programmable delay to ensure accurate data reading by allowing the amplified values from MRAM cells and reference cells to diverge sufficiently before comparison, thereby optimizing the timing of the enable signal for reliable data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the sense amplifier compares outputs immediately after read operation initiation, then the read speed is improved, but the accuracy of data reading deteriorates because the outputs have not sufficiently diverged
Solution Approach 1:
The patent applies preliminary action by introducing a delay mechanism that pre-calculates and prepares the optimal comparison timing based on historical data and process parameters. The system determines the required delay period in advance and uses this information to trigger the sense amplifier at the precise moment when outputs have sufficiently diverged, thus ensuring both speed and accuracy.
Solution Approach 2:
The patent implements dynamics by making the delay period adjustable rather than fixed. The delay can be dynamically modified based on process variations, temperature conditions, and device characteristics. This allows the system to adapt the comparison timing to match the actual divergence rate of outputs under different operating conditions, optimizing both speed and accuracy for each specific scenario.
2Measurement precision
If a delay is introduced to allow outputs to diverge sufficiently, then the data reading accuracy is improved, but the read performance deteriorates due to slower operation
Solution Approach 1:
The patent applies parameter changes by systematically varying the delay period based on process parameters, temperature, and device characteristics. Instead of using a conservative fixed delay that slows all operations, the system adjusts the delay parameter dynamically to match actual conditions, ensuring sufficient divergence for accurate reading while minimizing the time penalty to maintain high read performance.
Solution Approach 2:
The patent implements feedback by using historical data from previous read operations and process monitoring information to continuously refine and optimize the delay period. The system learns from actual output divergence patterns and adjusts the delay parameter accordingly, ensuring that the delay is long enough for accurate reading but not excessively long to degrade performance.
3Reliability
If a fixed delay period is used to ensure accurate reading, then the reliability is improved, but the adaptability to process variations deteriorates
Solution Approach 1:
The patent implements dynamics by transforming the fixed delay period into a dynamic, adjustable parameter. The delay can be modified in real-time based on process variations, temperature changes, and device-specific characteristics. This maintains reading reliability across different conditions by ensuring sufficient output divergence while adapting to the specific requirements of each operating scenario.
Solution Approach 2:
The patent applies parameter changes by systematically adjusting the delay parameter based on process variations and device characteristics. Instead of relying on a single fixed value, the system modifies the delay parameter to match actual operating conditions, ensuring reliable reading across different process batches, temperatures, and device variants while maintaining adaptability to changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables accurate data reading from MRAM devices while minimizing read delays, improving the yield and reducing error rates by allowing for adjustable delays based on process variations and device responsiveness.
Implementation Method 1
data values in a magnetic resistance-based memory cell
Implementation Method 2
a first analog amplifier amplifies an output value of a selected MRAM cell
Data Source
AI summary
Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. In a particular embodiment, a circuit includes a sense amplifier, having a first input, a second input, and an enable input. A first amplifier coupled to an output of a magnetic resistance-based memory cell and a second amplifier coupled to a reference output of the cell also are provided. The circuit further includes a digitally-controllable amplifier coupled to a tracking circuit cell. The tracking circuit cell includes at least one element that is similar to the cell of the magnetic resistance-based memory. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit. The sense amplifier may generate an output value based on the amplified values received from the output of the magnetic resistance-based memory cell and the reference cell once the sense amplifier receives an enable signal from the digitally-controllable amplifier via the logic circuit.