CAM Learn Throughput Optimization via Key Cache

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Solution Overview

Problem

In high-speed network environments, content-addressable memory (CAM) learn requests can lead to duplicated entries when multiple requests occur within the CAM access latency period, causing performance issues due to the need to throttle learn requests, which compromises router performance.

Innovation Solution

A network device with a key generator, searching unit, and key cache is used to generate and store lookup keys, comparing them to prevent duplicate entries by issuing a search and learn command only when a match is not found in the cache, thereby reducing CAM learn requests and enhancing learn rate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple CAM learn requests are processed simultaneously, then the learn rate is improved, but duplicate entries are created causing performance degradation

Engineering Contradiction:
Improvelearn rateVSAvoidentry accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements a preliminary check mechanism using a learn request queue and a tracking data structure that records which flows are currently being learned. Before processing a CAM learn request, the system checks whether the flow is already in the learning process. This preliminary action prevents duplicate learn requests from being processed simultaneously, thereby maintaining entry accuracy while allowing high learn rates by queuing subsequent requests appropriately.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If learn requests are throttled to prevent duplicates, then entry accuracy is maintained, but router performance is compromised

Engineering Contradiction:
Improveentry accuracyVSAvoidrouter performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces an intermediary mechanism consisting of a learn request queue and a tracking data structure that mediates between incoming learn requests and the CAM learning process. This intermediary layer manages the timing and sequencing of learn requests, allowing multiple requests to be accepted and processed in an organized manner rather than being简单地 throttled. The intermediary ensures that duplicate requests are identified and handled appropriately while maintaining high router performance by processing legitimate requests without unnecessary delays.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If CAM access latency is reduced, then packet processing speed is improved, but the window for duplicate learn requests increases

Engineering Contradiction:
Improvepacket processing speedVSAvoidlearn rate control
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent implements a feedback mechanism where the system continuously monitors the status of ongoing learn requests through a tracking data structure. When a learn request is initiated, the system records the flow identifier and checks this record before accepting new learn requests for the same flow. This feedback loop provides real-time information about the learning state, enabling the system to make informed decisions about subsequent requests. The feedback mechanism works effectively regardless of CAM access latency, as it operates at the request management level rather than being dependent on the physical access time to CAM.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9559987B1Method and apparatus for improving CAM learn throughput using a cache
Publication Date: 2017.01.31 TELLABS OPERATIONS
  • US9559987B1 patent drawing
  • US9559987B1 patent drawing
  • US9559987B1 patent drawing

AI summary

An apparatus and method of using a cache to improve a learn rate for a content-addressable memory (“CAM”) are disclosed. A network device such as a router or a switch, in one embodiment, includes a key generator, a searching circuit, and a key cache, wherein the key generator is capable of generating a first lookup key in response to a first packet. The searching circuit is configured to search the content of the CAM to match the first lookup key. If the first lookup key is not found in the CAM, the key cache stores the first lookup key in response to a first miss.