Bit Line Pre-Charge Timing Control for Flash Memory Peak Current Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash storage devices experience higher peak and average currents during the middle of a program operation due to increased inter-bit line capacitances and fast voltage ramping rates, leading to voltage drops and impacting write performance.
Innovation Solution
A controller in the storage device adjusts bit line pre-charging based on data latch counts, using different ramp rates and target voltages during various phases of the program operation to balance power consumption and write performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fast voltage ramping rates are used during program operation, then write performance is improved, but peak current increases causing voltage drops
Solution Approach 1:
The patent applies dynamics by making the bit line pre-charge timing flexible rather than fixed. The controller dynamically adjusts when to pre-charge bit lines based on the number of data latches being programmed, selecting from multiple possible timing options (before program pulse, during program pulse, or after program pulse). This dynamic adaptation allows the system to optimize between write performance and peak current management for different programming scenarios.
Solution Approach 2:
The patent changes the timing parameter of bit line pre-charge operation based on the data latch count. By modifying when the pre-charge occurs relative to the program pulse timing, the system can control the ramp rate characteristics and manage peak current while maintaining acceptable write performance. This parameter adjustment resolves the contradiction between fast writing and current management.
2Stability of the object's composition
If bit lines are pre-charged earlier to reduce peak current, then voltage stability is improved, but write performance may be impacted
Solution Approach 1:
The patent makes the pre-charge timing dynamic rather than fixed, allowing the system to adapt between voltage stability and write performance needs. By selecting from multiple timing options based on the programming context, the system can achieve voltage stability when needed while preserving write performance when possible.
Solution Approach 2:
The patent changes the timing parameter of bit line pre-charge based on the number of data latches being programmed. This parameter adjustment allows the system to optimize voltage stability for small latch counts while maintaining write performance for larger latch counts, resolving the contradiction between these two requirements.
3Device complexity
If fixed pre-charge timing is used, then device complexity is reduced, but adaptability to different programming scenarios is limited
Solution Approach 1:
The patent implements a dynamic control mechanism that adapts pre-charge timing based on the number of data latches being programmed. This dynamic approach provides adaptability to different programming scenarios while maintaining reasonable device complexity through systematic control logic.
Solution Approach 2:
The patent changes the pre-charge timing parameter based on the data latch count, providing adaptability to different programming scenarios. This parameter-based adaptation allows the system to respond to varying programming conditions without requiring complex structural modifications.
Data Source
AI summary
Aspects of a storage device including a memory and a controller are provided which allow for reduction of current during program operations using pre-charge timing control based on an inhibit bit line count acquired from data latches. When the inhibit bit line count is within a bit line count range, the controller pre-charges bit lines in memory during a first time period to a first target voltage, and when the inhibit bit line count is outside the bit line count range, the controller pre-charges the bit lines during a second, earlier time period to a second, smaller target voltage. The controller is thus configured to reduce current and minimize operation overlaps in the earlier time period during the middle of the program operation where current is highest. Thus, a balance in power consumption and performance may be achieved during program operations using timing control.