Dual Rail Memory Architecture Level Shifting Optimization
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Solution Overview
Problem
Dual-rail memory architectures face inefficiencies due to high power consumption and area usage by level shifters, which are slow and required for voltage level transitions between power domains in eDRAMs, leading to increased decoupling capacitors and overall power consumption.
Innovation Solution
Operational voltage levels are managed within the VDD power domain, enabling local voltage level shifting at the sense amplifying stage, reducing the need for level shifters and decoupling capacitors, and allowing most circuits to operate at lower voltage levels, thereby minimizing power consumption and circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If level shifters are used to transfer signals from lower power domain to higher power domain, then voltage level transition is enabled, but die area increases and power consumption increases
Solution Approach 1:
The patent extracts the level shifting function from dedicated level shifter circuits and relocates it to the sense amplifying stage. By integrating voltage level adaptation into the sense amplifier operation, the design eliminates separate level shifter blocks, thereby reducing die area while maintaining the necessary voltage level transition capability between power domains.
Solution Approach 2:
The sense amplifier is designed to perform multiple functions: it not only amplifies the differential signal from memory cells but also performs voltage level shifting from the lower VDD domain to the higher VDDM domain. This multi-functional approach consolidates circuitry and reduces the overall die area by eliminating dedicated level shifting components.
2Adaptability or versatility
If level shifters are placed at IO boundary to transfer signals between power domains, then signal transfer is enabled, but power consumption increases
Solution Approach 1:
The patent removes the power-consuming level shifter circuits from the IO boundary and integrates the level shifting function into the sense amplifier. This extraction eliminates the continuous power consumption associated with dedicated level shifters while maintaining the ability to transfer signals between power domains through the sense amplifier's inherent voltage switching capability.
Solution Approach 2:
The sense amplifier performs voltage level switching periodically only when needed for read/write operations, rather than maintaining continuous power consumption. The high voltage domain is activated temporarily during sense amplifying operations, reducing overall power consumption compared to continuously active level shifters at the IO boundary.
3Ease of operation
If most circuits operate at higher voltage level from level shifter, then signal transfer is simplified, but power consumption increases
Solution Approach 1:
The patent applies different voltage levels to different parts of the circuit based on their functional requirements. The sense amplifier and associated circuits temporarily operate at the higher VDDM voltage level only when signal transfer is needed, while the rest of the memory macro continues to operate at the lower VDD voltage level. This localized voltage application reduces overall power consumption while maintaining ease of operation where required.
4Reliability
If decoupling capacitors are added for high power domain, then power supply stability is improved, but die area increases
Solution Approach 1:
The patent extracts the high voltage domain operation from a separate, continuously powered domain and integrates it into the sense amplifier that operates temporarily only when needed. This eliminates the need for dedicated decoupling capacitors for a permanent high voltage domain, reducing die area while maintaining power supply stability through on-demand voltage switching.
Data Source
AI summary
A memory macro comprises a plurality of memory cells, a plurality of first amplifying circuits, a first driver circuit, and a first level shifter. The plurality of memory cells is arranged in groups of a first direction and groups of a second direction. Each amplifying circuit is coupled to a plurality of first memory cells arranged in a first group of the first direction via a first data line. The first driver circuit is configured to drive the plurality of first amplifying circuits. The first level shifter is configured to level shift an input signal operating in a first power domain to an output signal operating in a second power domain. The output signal of the first level shifter is for use by the first driver circuit. The first driver circuit and a sense amplifier of an amplifying circuit operate in the second power domain.