Split Local Data Bus for DRAM Bandwidth
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Solution Overview
Problem
Current DRAM chip architectures face challenges in increasing bandwidth without increasing the number of local data bus lines, which limits their performance as workload and speed demands rise.
Innovation Solution
The implementation of a split local data bus, where the local data bus is physically divided into two parts, allowing data to be directed in parallel to both sides of the bus, effectively doubling the prefetch width without increasing the number of local data bus tracks, thereby enhancing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of local data bus lines is increased to increase bandwidth, then bandwidth is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The local data bus is segmented into two separate parts: a first local data bus and a second local data bus. This segmentation allows data to be transmitted through parallel paths, effectively doubling the bandwidth without increasing the overall complexity of the bus architecture. Each bus handles a portion of the data traffic, reducing the burden on any single bus while maintaining high throughput.
Solution Approach 2:
The patent introduces a dimensional change by splitting the data transmission path into two distinct spatial dimensions (first local data bus and second local data bus). This allows data to flow simultaneously through multiple dimensions rather than being constrained to a single linear path, thereby increasing bandwidth without proportionally increasing the number of bus lines in any one dimension.
2Productivity
If the prefetch width is doubled to increase bandwidth, then bandwidth is improved, but the number of local data bus tracks must double
Solution Approach 1:
The prefetch operation is segmented across two separate local data buses. The first local data bus handles a portion of the prefetch data while the second local data bus handles another portion. This segmentation enables the system to achieve double prefetch width by distributing the data across two buses rather than requiring a single bus with doubled track count.
Solution Approach 2:
The patent merges the functionality of two separate local data buses to achieve the effect of a single bus with doubled capacity. By combining the data transmission capabilities of the first and second local data buses, the system achieves double prefetch width while maintaining the same number of physical bus tracks, as the two buses share the existing infrastructure.
3Speed
If the average distance from bitline sense amplifiers to global data bus is reduced to improve performance, then speed is improved, but the physical layout complexity increases
Solution Approach 1:
The data path is segmented into two separate routes through the first and second local data buses. This segmentation creates multiple shorter transmission paths from bitline sense amplifiers to the global data bus, reducing the average transmission distance. By distributing data across two buses, the system achieves shorter path lengths without requiring a completely reconfigured physical layout.
Solution Approach 2:
The patent introduces an additional spatial dimension for data transmission by utilizing two separate local data buses. This dimensional change allows data to travel through alternative paths that are physically shorter on average, reducing transmission distance and improving speed while maintaining a manageable physical layout through systematic bus arrangement.
Data Source
AI summary
Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.


