Memory Apparatus Dynamic Address Access Time Control
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Solution Overview
Problem
Conventional dynamic memory systems face challenges in accurately estimating address accessing time due to time delays caused by redundant device comparators, leading to potential performance issues with either overly long or short access times during data reading/writing.
Innovation Solution
A memory apparatus is designed with a mimic redundant device comparator, a reference delay signal generator, and a signal comparison controller to dynamically adjust address accessing time by comparing the time difference between the comparison signal and reference delay signals, allowing for the generation of a delay control signal to set the optimal accessing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the address accessing time is set to be overly long to account for redundant device comparator delay, then the reliability of memory access is improved, but the read/write performance of the memory apparatus deteriorates
Solution Approach 1:
The patent applies dynamics by making the address accessing time adjustable rather than fixed. The system dynamically determines the optimal accessing time based on actual test results, allowing it to adapt between reliability and performance requirements. The accessing time can be modified through control signals based on measured delay characteristics of the redundant device comparator.
Solution Approach 2:
The patent changes the parameter of address accessing time from a static value to a dynamically adjustable parameter. By measuring the actual delay of the redundant device comparator during testing, the system determines an optimal accessing time that balances reliability and performance, rather than using a fixed overly conservative value.
2Productivity
If the address accessing time is set to be overly short to improve read/write performance, then the productivity is improved, but erroneous actions of accessing the memory apparatus are likely to occur
Solution Approach 1:
The system dynamically determines the optimal accessing time based on actual measurements of the redundant device comparator's delay characteristics. This dynamic adjustment ensures that the accessing time is neither overly conservative nor too short, but optimally tuned to prevent erroneous actions while maintaining good performance.
Solution Approach 2:
The patent implements feedback by measuring the actual delay of the redundant device comparator during testing and using this measurement to determine the optimal accessing time. The feedback loop ensures that the accessing time is accurately calibrated to the actual hardware characteristics, preventing erroneous access actions.
3Device complexity
If the address accessing time is determined by simulation at the design stage, then the device complexity is reduced, but the measurement precision of accessing time is insufficient due to time delay variations
Solution Approach 1:
The patent uses a mimic redundant device comparator that copies the essential delay characteristics of the actual redundant device comparator. This mimic component allows the system to measure and characterize the delay behavior during testing without requiring complex simulation models, improving measurement precision while keeping the testing apparatus relatively simple.
Solution Approach 2:
The patent replaces complex simulation-based time estimation with a practical measurement approach using a mimic comparator during hardware testing. This substitution of simulation with physical measurement (using identical or similar circuitry) provides more accurate delay characterization that reflects actual hardware behavior under real conditions.
Data Source
AI summary
A memory apparatus includes a mimic redundant device comparator, a reference delay signal generator, and a signal comparison controller. The mimic redundant device comparator is configured to receive an input signal and to delay the input signal according to a mimic delay, so as to generate a comparison signal. The reference delay signal generator is configured to receive the input signal and to delay the input signal according to a plurality of reference delays, so as to generate a plurality of reference delay signals. The signal comparison controller is configured to receive the reference delay signals and the comparison signal. According to a time difference between the comparison signal and the reference delay signals, the signal comparison controller is configured to generate a selected signal and to generate a delay control signal according to the selected signal.