Row Decoder and Word Line Driver Voltage Management
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Solution Overview
Problem
Existing row decoder and word line driver designs face challenges with channel hot carrier (CHC) damage, slow switching times, high power consumption, and excessive gate-induced drain leakage (GIDL) as memory densities increase, making it difficult to accommodate CHC protection transistors and efficiently drive word lines in memory devices.
Innovation Solution
The design incorporates a row decoder and word line driver that eliminates the need for a CHC protection transistor by using separate power supply voltages to minimize CHC and GIDL issues, with a PMOS output transistor separate from the latch, allowing faster operation and reduced power consumption by dividing the word line driver into sections and applying different voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a CHC protection transistor is added to protect against channel hot carrier damage, then transistor reliability is improved, but device area increases and manufacturing complexity increases
Solution Approach 1:
The patent extracts and eliminates the CHC protection transistor from the decoder circuit by redesigning the transistor sizing and voltage distribution. The protection function is integrated into the existing decoder transistors through proper dimensioning rather than adding a separate protection device, thereby removing the complexity while maintaining reliability.
Solution Approach 2:
The patent changes the voltage parameters and transistor sizing parameters to inherently protect against CHC damage. By adjusting the voltage levels across different transistor sections and optimizing the width-to-length ratios, the design achieves CHC protection without requiring additional protection transistors, thus resolving the contradiction between reliability and complexity.
2Speed
If transistor size is increased to reduce switching time, then switching speed is improved, but power consumption increases and channel hot carrier damage worsens
Solution Approach 1:
The patent segments the decoder circuit into multiple transistor stages with different sizing optimizations. Each stage is sized appropriately for its specific function, allowing fast switching where needed while consuming less power in other stages. This segmented approach avoids the need to uniformly increase all transistor sizes, thereby achieving fast switching without excessive power consumption.
Solution Approach 2:
The patent applies different transistor sizing strategies to different parts of the circuit based on local requirements. Critical switching transistors are sized for speed, while other transistors are sized for power efficiency. This local optimization resolves the contradiction by allowing fast switching in specific locations without increasing overall power consumption across the entire decoder.
3Speed
If transistor size is increased to reduce switching time, then switching speed is improved, but channel hot carrier damage increases
Solution Approach 1:
The patent changes the voltage parameters across different transistor stages to reduce the drain-to-source voltage stress that causes CHC damage. By optimizing the voltage distribution and transistor sizing simultaneously, the design achieves fast switching speeds while keeping the electric field stress below thresholds that cause significant hot carrier injection, thus resolving the contradiction between speed and CHC damage.
4Speed
If voltage levels are increased to improve switching performance, then switching speed is improved, but gate-induced drain leakage increases
Solution Approach 1:
The patent optimizes the voltage parameters to achieve the minimum necessary voltage levels for fast switching while avoiding excessive voltages that cause GIDL. By carefully tuning the voltage distribution across the decoder stages and matching it with appropriate transistor sizing, the design achieves fast switching performance while minimizing gate-induced drain leakage currents.
Data Source
AI summary
Address decoders and access line drivers are provided. One such row decoder and access line driver receives power supply voltages in a manner that prevents CHC damage and avoids GIDL currents in transistors in the decoder and driver. The row decoder and a latch in the driver are powered by a first supply voltage, and an output stage in the access line driver is powered by a second supply voltage. The first and second supply voltages are maintained at a relatively low level during standby before an address is decoded. Only after an address is decoded to set the latch are the supply voltages increased to levels needed to drive the access line. Further, before resetting the latch, the first and power supply voltages are decreased to their standby levels. By maintaining the first and second voltages relatively low until after the latch is set and reset, GIDL currents may be avoided and CHC damage may be prevented.