Dynamic Output Delay Selection in Memory Control Devices
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Solution Overview
Problem
Existing memory control devices for DDR3 and DDR4 SDRAMs require complex circuitry and significant power to insert bit-level granularity delays, which complicates the compensation for skews in the PCB connecting the memory control device to SDRAM devices, leading to inefficiencies in signal alignment and increased implementation area and power consumption.
Innovation Solution
A memory control device with an output circuit and output delay unit that dynamically selects output delays by combining a de-skew delay common across ranks and a write-levelization delay unique to each rank, using a write-levelization delay controller and multiplexer circuit to adjust delays for each write transaction, thereby simplifying the circuitry and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If complex circuitry is used to insert bit-level granularity delays for skew compensation, then signal alignment precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The delay compensation function is segmented into two independent parts: a common de-skew delay applied to all ranks and rank-specific write-levelization delays. This segmentation allows each part to be optimized separately, reducing overall circuit complexity while maintaining precision. The common delay handles bulk alignment needs, while individual delays handle rank-specific adjustments.
Solution Approach 2:
The delay values are made dynamic and adjustable rather than fixed. The memory control device can programmatically set different delay values for different ranks and transactions, allowing adaptive optimization without requiring complex hardwired circuitry for each possible delay configuration.
2Manufacturing precision
If complex circuitry is used to insert bit-level granularity delays for skew compensation, then signal alignment precision is improved, but power consumption increases
Solution Approach 1:
By segmenting the delay compensation into common and rank-specific components, the circuit can activate only the necessary delay paths for each transaction. This reduces simultaneous switching activity and power consumption compared to a fully complex delay network that must always be fully operational.
Solution Approach 2:
The delay parameters are made programmable and adjustable, allowing the system to optimize power consumption by setting appropriate delay values for different operating conditions and ranks, rather than requiring maximum-capability circuitry to be always active.
3Manufacturing precision
If significant IC area is allocated for delay circuitry, then output delay precision is improved, but implementation area increases
Solution Approach 1:
The delay circuitry is segmented into shared common delay resources and smaller rank-specific delay resources. This allows precise delay control to be achieved with less total area than a fully redundant approach, as the common resources serve multiple ranks while rank-specific resources handle only their designated ranks.
Solution Approach 2:
The common de-skew delay circuitry serves as a universal resource for all ranks, eliminating the need for separate full-delay circuits for each rank. This multi-functionality reduces the total IC area required while maintaining the precision needed for skew compensation across all ranks.
4Device complexity
If fixed delay values are used for all ranks, then device complexity is reduced, but adaptability to different rank configurations decreases
Solution Approach 1:
The delay values are made dynamic and programmable, allowing the memory control device to adapt to different rank configurations, PCB variations, and SDRAM device characteristics. This dynamic adjustment capability provides high adaptability while keeping the control logic relatively simple through systematic delay management.
Solution Approach 2:
The delay parameters can be changed and optimized for different operating conditions and rank configurations. This parameter adjustability enables the system to adapt to various scenarios without requiring fundamentally different circuit architectures, balancing simplicity with versatility.
Data Source
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AI summary
In an example, a memory control device (104) includes an output circuit (310), an output delay unit (312), and a write-levelization controller (302). The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system (106) having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write- levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions.