I/O Line Sense Amplifier Voltage Segmentation

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Solution Overview

Problem

Conventional I/O line sense amplifiers in semiconductor memory devices face challenges in reducing operating current while maintaining sufficient signal amplification, leading to increased column address access time and power consumption.

Innovation Solution

The proposed solution involves an I/O line sense amplifier configuration that includes a buffer unit driven by a first level voltage, a sense amplifier driven by a second level voltage, and a precharge unit driven by the first level voltage, with a metal oxide semiconductor (MOS) transistor equalizer to short-circuit output lines, reducing operating current and improving signal amplification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a one-stage amplification type I/O line sense amplifier is used, then the current consumption is decreased, but the offset characteristic of the input signal is deteriorated and the column address access time increases

Engineering Contradiction:

Improvecurrent consumptionVSAvoidcolumn address access time

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The I/O line sense amplifier is divided into two separate amplification stages: a first sense amplifier that amplifies the local I/O line signal, and a second sense amplifier that amplifies the output of the first stage. This segmentation allows each stage to operate with optimized parameters, achieving both low power consumption and fast operation by distributing the amplification task across multiple simpler stages rather than requiring one complex high-gain stage

Inventive Principle:

Principle #1Segmentation

2Measurement precision

If a two-stage amplification type I/O line sense amplifier is used, then the offset characteristic is improved, but the current consumption increases

Engineering Contradiction:

Improveoffset characteristicVSAvoidcurrent consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

Different voltage levels are applied to different parts of the two-stage amplifier system. The first sense amplifier operates at a first voltage level optimized for low-power local signal amplification, while the second sense amplifier operates at a second voltage level optimized for driving the global I/O line. This local quality differentiation allows each stage to consume minimal power while achieving the required performance for its specific function

Inventive Principle:

Principle #3Local quality

3Reliability

If the potential difference between data on local I/O lines is increased, then sufficient signal amplification is achieved, but the column address access time increases due to delayed strobe signal enabling

Engineering Contradiction:

Improvesignal amplification sufficiencyVSAvoidcolumn address access time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The first sense amplifier performs preliminary amplification of the local I/O line signal before it is passed to the second sense amplifier. This preliminary action boosts the signal level early in the amplification chain, allowing the second stage to operate with reduced gain requirements and enabling faster strobe signal timing without sacrificing amplification sufficiency

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS7821857B2Input/output line sense amplifier and semiconductor memory device using the same

Publication Date: 2010.10.26 SK HYNIX INC

AI summary

An input/output (I/O) line sense amplifier includes a buffer unit, a sense amplifier, and a precharge unit. The buffer unit is driven by a first level voltage to buffer a strobe signal, and the sense amplifier is driven by a second level voltage to amplify a signal of an I/O line in response to an output signal of the buffer unit. The precharge unit is driven by the first level voltage to precharge an output signal of the sense amplifier in response to the output signal of the buffer unit.