Memory Interface Timing Adjustment Circuit for Phase Noise
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Solution Overview
Problem
In high-speed data transmission systems like DDR-SDRAM, phase changes due to variations in operation voltage and temperature can cause pulse-shaped noise in data strobe signals, leading to incorrect data reception, especially when the data strobe signal enters a high impedance state, affecting the synchronization between the data strobe and gate signals.
Innovation Solution
A timing adjustment circuit is implemented in the memory interface, comprising a gate circuit, original gate signal generation, high impedance prevention, and gate leveling circuit, which adjusts the phase of the gate signal to optimize its timing with respect to the data strobe signal, preventing high impedance states and correcting phase shifts dynamically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data strobe signal enters into high impedance state during idle periods, then power consumption is reduced and signal integrity is improved, but pulse-shaped noise occurs due to crosstalk influence when transitioning to active state
Solution Approach 1:
The patent applies preliminary action by outputting a preamble signal before the actual data strobe signal when transitioning from high impedance to active state. This preamble signal prepares the transmission line and prevents pulse-shaped noise by establishing proper signal levels beforehand, thus resolving the contradiction between maintaining high impedance for signal integrity and avoiding noise during state transitions.
2Device complexity
If the gate signal phase is fixed according to nominal latency, then device complexity is reduced, but phase misalignment occurs due to voltage and temperature variations in high-speed transmission
Solution Approach 1:
The patent implements feedback by detecting the actual phase relationship between the data strobe signal and the gate signal, and adjusting the gate signal phase based on detected timing information. This feedback mechanism ensures accurate data reception despite voltage and temperature variations, resolving the contradiction between simple fixed-phase control and reliable data reception in high-speed transmission.
Solution Approach 2:
The patent applies dynamics by making the gate signal phase adjustable and adaptive rather than fixed. The system dynamically adjusts the gate signal timing based on detected phase relationships and operating conditions, enabling reliable high-speed data reception while managing the complexity through structured adjustment mechanisms.
3Reliability
If the gate signal timing is adjusted to compensate for phase variations, then data reception accuracy is improved, but device complexity increases due to additional timing adjustment circuits
Solution Approach 1:
The patent applies self-service by enabling the system to automatically detect and adjust its own timing parameters without external intervention. The timing adjustment circuit self-calibrates by detecting the phase relationship between signals and automatically adjusting gate signal timing, improving data reception accuracy while managing complexity through autonomous operation.
Data Source
AI summary
According to one embodiment, a timing adjustment circuit for a memory interface is presented. The circuit is provided with a gate circuit, an original gate signal generation circuit, a high impedance prevention unit, an impedance control unit and a gate leveling circuit. The gate circuit performs gating of a data strobe signal outputted from a memory. The original gate signal generation circuit generates an original gate signal based on information of a read latency and a burst length. The high impedance prevention unit to prevent the data strobe signal from being in a high impedance state. The impedance control unit controls execution and release of operation of the high impedance prevention unit. The gate leveling circuit outputs a timing adjusted gate signal to the gate circuit based on the original gate signal and the data strobe signal.