Non-Volatile Memory Write Timing Control Circuit
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Solution Overview
Problem
Current non-volatile memory technologies, such as flash memory, face challenges with high power consumption, complex integration, and slow write speeds, necessitating the development of more compatible and efficient memory solutions for portable electronic devices.
Innovation Solution
A write timing control circuit for non-volatile memory that includes a memory cell, a resistance state monitoring unit, and a write timing generating unit, which monitors resistance state switching during write operations and generates optimal write timing using clock and control signals to reduce power consumption by disabling the timing control line when the write operation is complete.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the timing control line remains enabled throughout the clock cycle, then the memory cell can complete its write operation, but power consumption increases due to unnecessary continued enablement
Solution Approach 1:
The patent employs a feedback mechanism where the resistance state monitoring unit continuously monitors the memory cell's resistance state during the write operation and provides feedback signals to the write timing generating unit. This feedback loop enables the system to dynamically adjust the timing control line enablement based on the actual write operation status, turning off the timing control line immediately when the write operation completes, thus eliminating unnecessary power consumption while ensuring reliable write operation completion.
Solution Approach 2:
The patent implements dynamic timing control where the write timing generating unit generates write timing signals that adaptively control the timing control line based on real-time monitoring of the write operation progress. Instead of a static fixed-duration enablement, the system dynamically adjusts the enablement duration to match the actual write operation duration, preventing both premature termination and excessive continuation of the timing control line enablement.
2Loss of energy
If the timing control line is disabled immediately after write operation starts, then power consumption is reduced, but the write operation cannot complete
Solution Approach 1:
The resistance state monitoring unit provides continuous feedback during the write operation, enabling the write timing generating unit to maintain the timing control line enablement for the exact duration needed to complete the write operation. The system monitors resistance state changes and keeps the timing control line enabled until the write operation is confirmed complete, ensuring productivity is not compromised while minimizing unnecessary power consumption.
Solution Approach 2:
The write timing generating unit generates the write timing signal in advance based on the clock signal and initial conditions, ensuring the timing control line is enabled at the precise moment needed for the write operation to start. This preliminary timing generation ensures that the write operation has sufficient time to complete while avoiding any delay that would waste power.
3Reliability
If conventional flash memory is used, then non-volatile data storage is achieved, but write speed is slow and integration with logic process is difficult
Solution Approach 1:
The patent utilizes RRAM technology which fundamentally changes the physical parameters of the memory cell, specifically using resistance state changes instead of charge storage. This parameter change enables faster write speeds because resistance state switching in RRAM occurs much more rapidly than the charge trapping/detrapping process in flash memory. The resistance-based storage mechanism also enables lower write voltages and better integration with standard logic processes.
Solution Approach 2:
The patent replaces the charge-based storage mechanism of flash memory with a resistance-based mechanism in RRAM. This substitution changes the fundamental operating principle from electrical charge accumulation to resistance state switching, which enables faster operation speeds and lower power consumption while maintaining non-volatile data storage capability.
4Reliability
If conventional flash memory is used, then non-volatile data storage is achieved, but integration with logic process is complex
Solution Approach 1:
By changing from charge-based to resistance-based storage, the patent enables compatibility with standard CMOS logic processes. RRAM cells can be fabricated using existing semiconductor manufacturing processes without requiring the complex additional process steps that flash memory integration demands, thereby reducing device complexity while maintaining non-volatile storage capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient power management by immediately turning off the timing control line after the write operation is finished, thereby reducing unnecessary power consumption and enhancing the compatibility and speed of write operations in non-volatile memory systems.
Implementation Method 1
A write timing control circuit of a non-volatile memory is provided, which includes at least one memory cell, at least one resistance state monitoring unit and at least one write timing generating unit. The memory cell stores data states with different resistance states.
Data Source
AI summary
A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory cell stores data states with different resistance states. A write timing is input to the memory cell through a timing control line. Next, the write timing is generated based on a clock signal and the control signal. The write timing is enabled at the beginning of a cycle of the clock signal, and is disabled when the memory cell finishes the resistance state switching.