Redundant Memory Data Correction for Radiation Hardening

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Solution Overview

Problem

Electronic systems operating in high radiation environments, such as aerospace and defense applications, are susceptible to transient upset events caused by high energy ionizing particles, which can corrupt data stored in memory devices, leading to system malfunctions and errors.

Innovation Solution

A redundant data storage system with multiple memory devices and an error detection and correction circuit that detects data mismatches and generates a correction signal to write the majority state of the data into memory devices, ensuring data integrity even in the presence of transient upset events.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If redundant data storage is implemented to mitigate data corruption from radiation, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata integrityVSAvoidmemory system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements redundant data storage by creating multiple copies of the same data across three separate memory devices. This copying approach allows the system to store identical data in triplicate, enabling error detection and correction through comparison of the copies without requiring complex encoding schemes.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent divides the redundant storage system into three separate memory devices rather than using a single complex memory unit. Each memory device independently stores a copy of the data, and the error detection circuit segments the comparison function to identify which specific memory device contains corrupted data, thereby simplifying the overall system architecture.

Inventive Principle:
Principle #1Segmentation

2Reliability

If multiple memory devices are used for redundant storage, then reliability is improved, but loss of time increases due to detecting and correcting errors

Engineering Contradiction:
Improvedata integrityVSAvoiderror detection and correction time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The error detection circuit continuously monitors the data stored in all three memory devices without requiring system interruption. By maintaining continuous comparison of the redundant copies, the system can detect errors immediately when they occur rather than waiting for periodic checks, thereby minimizing time loss while maintaining high reliability.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The system performs self-diagnosis through the error detection circuit that automatically compares the three data copies and identifies mismatches without external intervention. The error correction circuit then autonomously corrects the corrupted data by selecting the majority value, enabling the system to self-heal without requiring external error handling procedures that would consume additional time.

Inventive Principle:
Principle #25Self-service

3Reliability

If error detection and correction circuits are added, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata integrityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The error detection and correction functionality is achieved by copying and comparing the three stored data versions rather than implementing complex error-correcting codes. This approach uses simple majority logic to determine the correct data value, avoiding the need for sophisticated mathematical algorithms and reducing circuit complexity while maintaining high reliability.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS12119074B2Data correction of redundant data storage
Publication Date: 2024.10.15 TEXAS INSTRUMENTS INC
  • US12119074B2 patent drawing
  • US12119074B2 patent drawing
  • US12119074B2 patent drawing

AI summary

In one example, an apparatus comprises first, second and third memory devices, an error detection circuit, and an error correction circuit. The error detection circuit is configured to detect a mismatch among data stored at the first, second, and third memory devices, and responsive to detecting the mismatch, provide a correction signal representing a majority state of the data. The error correction circuit is configured to write the majority state of the data into at least one of the first, second, or third memory devices responsive to the correction signal.