Semiconductor Memory Device Sub Word Line Voltage Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in preventing read disturbances due to overshooting cell currents during the reading process, particularly when the voltage of the sub word line is raised in a single stage, leading to increased probabilities of read disturbances.
Innovation Solution
The semiconductor memory device employs a two-stage voltage application method for the sub word line or sub local column control line, initially setting the voltage to a lower level to manage coupling noise and then increasing it to a higher level after the global bit line is charged, thereby maintaining stable current flow and preventing overshoot.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the voltage of the sub word line is raised in a single stage to a high level, then the charging speed of the global bit line is improved, but the cell current overshoots causing read disturbances
Solution Approach 1:
The voltage application process is segmented into two distinct stages: a first period with a first voltage level and a second period with a second voltage level. This temporal segmentation allows the system to charge the global bit line efficiently in the first stage while preventing cell current overshoot in the second stage, thus resolving the contradiction between speed and reliability.
Solution Approach 2:
The patent implements periodic voltage application to the sub word line, alternating between a first voltage during a first period and a second voltage during a second period. This periodic action enables controlled charging phases followed by stabilization phases, preventing continuous high current flow that causes read disturbances while maintaining overall charging efficiency.
2Reliability
If the voltage of the sub word line is kept at a low level to prevent cell current overshoot, then read disturbances are suppressed, but the charging speed of the global bit line decreases
Solution Approach 1:
By dividing the voltage application into segmented periods with different voltage levels, the system can achieve both fast charging (during the first period with higher voltage) and read disturbance prevention (during the second period with lower voltage), resolving the contradiction between speed and reliability.
Solution Approach 2:
The periodic switching between first and second voltage levels allows the system to alternate between aggressive charging phases and stabilization phases, ensuring that the global bit line charges quickly while cell current overshoot is prevented during the second period.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses read disturbances by ensuring the cell current remains within safe limits, even during charging, without compromising the speed of charging the global bit line, thus enhancing the reliability of data retrieval.
Implementation Method 1
A magnetic random access memory (MRAM) is a memory device which uses, as a memory cell for storing information, a memory element having the magnetoresistamce effect.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a first memory cell including a first resistance change memory element and a first transistor, a first word line electrically coupled to a control terminal of the first transistor, and a first circuit configured to, in a reading, apply a first voltage to the first word line during a first period and apply a second voltage higher than the first voltage to the first word line during a second period after the first period.