3D Memory Block Pitch Layout for Edge Defect Reliability
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Solution Overview
Problem
The integration degree of semiconductor devices with memory cells stacked in a 3D manner faces limitations due to fabrication defects and structural instability, particularly at the edge regions where memory blocks are more prone to defects during the manufacturing process.
Innovation Solution
The semiconductor device incorporates memory blocks with varying block pitches, where blocks closer to the edge have larger pitches than those in the center, and utilizes alternating stacks of conductive and insulating layers with specific slit structures to maintain structural stability and prevent defects, allowing for improved integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory blocks are arranged with uniform block pitch across the memory plane, then fabrication simplicity is maintained, but edge regions experience higher defect rates and reduced reliability
Solution Approach 1:
The patent applies local quality by configuring different block pitches for different regions of the memory plane. Specifically, a first block pitch is used for memory blocks in a first region and a second block pitch is used for memory blocks in a second region. This allows each region to have optimized parameters suited to its specific fabrication characteristics, with edge regions potentially receiving larger block pitches to compensate for higher defect rates during manufacturing.
2Manufacturing precision
If block pitch is increased to reduce fabrication defects at edge regions, then manufacturing precision improves, but integration density decreases
Solution Approach 1:
The patent implements local quality by applying different block pitch values to different regions of the memory plane. The first block pitch and second block pitch are configured based on the specific requirements of each region, allowing edge regions with higher defect susceptibility to have optimized spacing while central regions maintain tighter spacing for higher density.
Solution Approach 2:
The patent segments the memory plane into multiple regions (first region and second region) with different block pitch configurations. This segmentation allows independent optimization of each region's block pitch based on local fabrication characteristics, rather than applying a uniform pitch across the entire plane.
3Productivity
If 3D stacking is implemented to improve integration density, then productivity increases, but fabrication defects and reliability issues worsen
Solution Approach 1:
The patent applies local quality by configuring different block pitches for different regions of the memory plane. Specifically, a first block pitch is used for memory blocks in a first region and a second block pitch is used for memory blocks in a second region. This allows each region to have optimized parameters suited to its specific fabrication characteristics, with edge regions potentially receiving larger block pitches to compensate for higher defect rates during manufacturing.
Data Source
AI summary
A semiconductor device includes: a first memory block having a first block pitch; and a second memory block belonging to a same plane as the first memory block, the second memory block located closer to a plane edge than the first memory block, the plane edge being an edge of the plane, wherein the second memory block has a second block pitch that is larger than the first block pitch.