3D Memory Substrate Insulating Layer Layout for Edge Reliability
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and maintaining electrical properties and reliability, particularly in three-dimensional memory cell configurations.
Innovation Solution
A semiconductor device design featuring a substrate with specific width, spacing, and pitch configurations for substrate insulating layers in different regions, along with channel and gate electrode structures, to enhance structural integrity and reduce defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are disposed three-dimensionally to increase data storage capacity, then data storage capacity is improved, but electrical properties and reliability deteriorate
Solution Approach 1:
The substrate insulating layers are configured with different widths, spacings, and pitches in different regions of the substrate. Specifically, the layers have a first width, first spacing, and first pitch in the center block region, and a second width, second spacing, and second pitch in the edge block region, where the second dimensions are larger than the first dimensions. This local differentiation optimizes electrical properties and reliability in different areas while maintaining three-dimensional memory cell configuration for high storage capacity.
2Ease of manufacture
If substrate insulating layers have uniform width and spacing across the substrate, then manufacturing is simplified, but electrical properties and reliability deteriorate
Solution Approach 1:
The substrate insulating layers are configured with different widths, spacings, and pitches in different regions of the substrate. Specifically, the layers have a first width, first spacing, and first pitch in the center block region, and a second width, second spacing, and second pitch in the edge block region, where the second dimensions are larger than the first dimensions. This local differentiation optimizes electrical properties and reliability in different areas while maintaining three-dimensional memory cell configuration for high storage capacity.
Data Source
AI summary
A semiconductor device includes a first semiconductor structure including a first substrate and circuit devices; and a second semiconductor structure including a second substrate on the first semiconductor structure and having a first region and a second region, gate electrodes in the first region and stacked in a first direction, and extending in the second region by different lengths in a second direction, channel structures extending by penetrating through the gate electrodes, separation regions penetrating through the gate electrodes, extending in the second direction, spaced apart from each other in a third direction, and defining a center block region and an edge block region, and substrate insulating layers in the second substrate between the separation regions in the second region. A width of the substrate insulating layers in the third direction is greater in the edge block region than in the center block region.