3D Semiconductor Memory Electrode Stacks for Integration Density

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Solution Overview

Problem

Three-dimensional semiconductor memory devices face challenges in increasing integration density and reliability due to structural configurations, which can degrade electrical characteristics and require high-cost equipment for pattern formation.

Innovation Solution

A three-dimensional semiconductor memory device design featuring an electrode structure with alternating stacks of electrodes and insulating patterns on a semiconductor substrate, including a vertical active pattern and a recessed region filled with insulating material, along with an electrode-dielectric layer extending to cover specific electrode surfaces, and a method of fabricating this structure by alternately stacking replacement and insulating layers, forming vertical active patterns, and replacing sacrificial layers with electrodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If three-dimensional semiconductor memory devices are fabricated with conventional electrode structures, then integration density can be increased, but electrical characteristics and reliability are degraded due to structural configurations

Engineering Contradiction:

Improveintegration densityVSAvoidelectrical characteristics

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The electrode structure is divided into multiple segments including a first electrode, second electrode, third electrode, and fourth electrode arranged in alternating stacks with insulating patterns. This segmentation allows each electrode to be independently optimized for electrical performance while maintaining high integration density through the vertical three-dimensional arrangement.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the electrode structure are assigned different materials and configurations tailored to local electrical requirements. For example, specific electrodes use materials with optimized conductivity and barrier properties, while insulating patterns are strategically placed to minimize interference and enhance signal integrity in critical areas.

Inventive Principle:

Principle #3Local quality

2Manufacturing precision

If fine patterns are formed to increase integration density, then manufacturing precision is improved, but process technology limitations and high equipment costs remain

Engineering Contradiction:

Improvepattern formation precisionVSAvoidfabrication cost

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent transitions from two-dimensional planar patterns to three-dimensional vertical structures by stacking electrodes and insulating patterns alternately. This dimensional change allows integration density to be increased through the vertical dimension rather than requiring ever-smaller lateral feature sizes, thereby avoiding the need for extremely expensive advanced lithography equipment.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Sacrificial layers are formed in advance before the final electrode structures are created. These sacrificial layers serve as temporary placeholders that guide the formation of the alternating electrode and insulating pattern stacks, and are subsequently removed to create the final desired structure. This preliminary action simplifies the overall fabrication process and reduces manufacturing complexity.

Inventive Principle:

Principle #10Preliminary action

3Device complexity

If conventional electrode structures are used, then device complexity is reduced, but etch damage occurs and electrical characteristics are degraded

Engineering Contradiction:

Improveelectrode structure complexityVSAvoidetch damage

Core Design Contradiction:

Device complexityVSObject-affected harmful factors

Solution Approach 1:

Protective layers are formed beforehand to cushion and protect the electrode structures during etching processes. These protective layers prevent direct exposure of sensitive electrode materials to harsh etchants, thereby minimizing etch damage while maintaining the integrity of the three-dimensional electrode configuration.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS9972638B2Methods of fabricating three-dimensional semiconductor devices

Publication Date: 2018.05.15 SAMSUNG ELECTRONICS CO LTD

AI summary

Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.