Solid-State Devices TRIZ Cases

Multiple small vias and a reflective common cathode grid reduce dark spots and improve power-efficient local dimming in LED displays.

Different-band-gap oxide channel layers in 3D memory raise on-current, cut leakage current, and improve bias stability.

Different charge accumulation counts across pixel groups expand dynamic range, preserving weak signals while preventing bright-region saturation.

Replacing red and green filters with yellow layers plus quantum dot conversion and a dielectric layer improves luminance, color gamut, and manufacturability.

A non-contact conductive shield layer overlapping the data line cuts coupling to the pixel electrode and improves display quality.

A dopant-free electron transport stack and charge generation layer improve electron injection in multi-emission OLEDs, cutting driving voltage.

Rheology-matched phosphor films enable one-step lamination of dual- and multi-color LEDs, reducing settling while improving color uniformity.

A separate bottom electrode, reflector, and coupling structure prevent oxide-induced electrical opens while preserving high reflectivity in micro display IC pixels.

Tuned metal-ligand OLED dopants balance HOMO/LUMO and triplet levels to deliver deep blue emission, high efficiency, and longer lifespan.

Varying nanowire diameters in single-step selective area epitaxy enables monolithic visible-spectrum emission from one InGaN/GaN LED chip.

An ALD-formed metal nitrate interfacial layer protects metal nitride electrodes from high-temperature impurity buildup and stabilizes capacitance.

A V-shaped trench and vertical transfer gate move photoelectrons efficiently to the floating diffusion region, reducing black dots and ghost images.

Angled RGB sub-pixel layout and asymmetric chamfering align brightness centers, cutting drive current demand and extending OLED lifetime.

Sidewall protrusions and support layers raise capacitor bottom electrode aspect ratio to increase memory capacity while improving reliability.

Prebuilt light-blocking structures are transferred with micro LEDs to avoid lithography damage and improve yield on temporary substrates.

A ring-shaped light blocking trench shields black reference sensors from lateral light, improving calibration accuracy and reducing noise.

Wafer-level 3D bonding simplifies SSL-to-PV alignment, improves light coupling, and scales compact high-voltage optical transformers.

Patterned recess fills with intermediate CTE materials reduce stress, delamination, and cracking in stacked semiconductor structures.

Dual-sided PCB mounting with a support through-hole reduces toner sensor size, avoids component interference, and maintains stable optical measurement.

An ET-region pad layout lowers local insulation height so the FPC fully contacts testing pads and the display substrate lights normally.

Rear-side etching and polishing expose a silicon via core for self-aligned electrode contact while preserving oxide insulation from the substrate.

A split source follower with one source and two drains cuts thermal and flicker noise in tightly integrated image sensor pixels.

Tailored Formula X emissive compounds tune OLED output for saturated deep blue, blue, and green light with improved color accuracy and efficiency.

Discrete-thickness micro-lenses improve micro-LED light extraction and collimation where smooth lens fabrication is difficult at very small pitch.

A thicker top spacer and thinner bottom spacer let raised source/drain regions stay close for drive current while limiting gate overlap capacitance.

Low-temperature vapor deposition with substrate bias smooths resistive memory layers, preserving ohmic contact continuity and region isolation.

Tungsten-based interconnects and stoichiometric passivation enable low-resistance polysilicon-monosilicon connections for harsh media.

Multiple anti-reflection layers tuned for different colored light cut glass-surface reflection and color shift to improve display contrast.

Replacing a photodiode with a photoelectric thin-film transistor maintains high quantum efficiency while reducing sensor size and process complexity.

Staggered body contacts isolated from source and drain reduce SOI floating body effects while improving linearity, breakdown voltage, and RF performance.

Expanded chip spacing, resin sealing, and offset stacking improve semiconductor packaging throughput while enabling stable compact mounting.

Rounded substrate corners spread bending stress in flexible OLED layers, reducing metal film breakage and extending display service life.

A pixel layout shifts charge holding and transfer sections toward the optical center to block oblique light, cutting noise and focal plane distortion.

Excess charge is split between overflow capacitors and a supply path to extend image sensor dynamic range while preserving sensitivity and lowering noise.

A convex dielectric reflection layer reduces blue shift in LED phosphor lighting, improving luminance uniformity and light use efficiency.

Multiple color LED structures are integrated on one PCB with independent driving, simplifying assembly while enabling compact high-resolution lighting.

Microlenses and a light-shielding layer improve fingerprint sensor photosensitivity while blocking oblique light that degrades imaging quality.

Dual-gate IGZO connections through stacked insulating layers boost LTPO driving speed while preserving the low leakage benefit of oxide transistors.

Merging the driving power bus line with the panel identification mark reduces unused space while minimizing voltage drop through a protective cladding unit.

A solid state resistive device employs a p-type poly-silicon electrode and amorphous silicon nanostructure to enable adjustable resistance states.

Direct eutective connections between LED chip electrodes and lead frames prevent open defects and improve luminescent efficiency by removing wire bond failures.

An organic gate insulating layer with a thickness of 1,800 to 2,500 angstroms improves mobility and on/off ratio in thin film transistors.

Concaves on the insulating interlayer embed glass cement to increase lateral tensile-resistance strength between OLED substrate and package.

Confining organic semiconductor deposition within a segmented bank structure prevents particle cross-talk and simplifies the patterning process.

A stacked image pickup device uses an electric potential adjusting electrode to maintain uniform charge collection, preventing image unevenness at pixel edges.

A metal layer bridges the thin transparent second electrode and an auxiliary electrode, reducing voltage drops caused by high resistivity.

A semiconductor device uses a bias circuit to reduce potential differences across unselected memory elements during write operations.

A laser ablation method creates openings in organic electroluminescent media to form electrical connections between upper electrodes and conductive bus lines.

Driving connected word lines with common voltage signals reduces RC delays and accelerates voltage ramp-up for faster memory access.

Fused polycyclic compounds enable thermally activated delayed fluorescence in light emitting devices.

A thin film transistor array panel uses a middle storage electrode overlapping the drain to form capacitance.

OLED array substrate merges adjacent subpixel light-emitting layers into continuous structures to increase aperture ratio.

A nonvolatile memory device uses a conductive upper electrode with lower main group element concentration than the recording layer to enable reversible resistance switching.

A semiconductor device integrates a network of diodes to provide bidirectional electrostatic discharge protection with low capacitance.

An intermediary resistance element between compensation regions and the source node reduces load current gradients during switching, minimizing voltage spikes.

Porous holes reduce thermal expansion of the high-conductivity substrate, while a moisture-blocking layer prevents ingress through those openings.

Composite emission layers with optimized heteroatom parameters resolve red light luminance stability trade-offs.

A 3D semiconductor memory device uses parallel conductive lines at different vertical levels to define intersections for memory cells.

Parallel coupling of switching transistors reduces contact resistance, shrinking device area and simplifying fabrication steps.

Steric shielding by large organic ligands protects labile copper clusters, maintaining stability against oxidation while preserving high luminescence intensity.

Segmenting the continuous metal layer into a mesh geometry resolves the contradiction between uniform current spreading and light extraction efficiency.

Flexible printed circuits connect optical packages to a planar lightwave circuit housing, accommodating thermal expansion differences.

A display device connecting element uses a composite adhesive layer to bond substrates and block moisture ingress.

Positioning an adhesive layer on non-overlapping insulating areas reduces applied force on light-emitting layers, preventing delamination under physical stress.

Aligned pixel definition and supporting blocks in OLED overlapped areas increase aperture ratio to resolve uneven brightness issues.

Tilted implantation creates edge doping peaks in poly resistors, making resistance insensitive to critical dimension variations.

F value 1.5 or less objective lens fades upper wire reflections while maintaining ball and chip surface image clarity.

Shared collector contacts in a bipolar select device increase drive current density, reducing the area required for each memory cell.

A PoP semiconductor package monitors chip temperatures to transfer data from hot banks to cold ones.

A ferroelectric memory device applies a controlled weak erase voltage to remove trapped electrons from the storage layer.

Oxidizing silicon nitride layers forms silicon oxynitride gate-to-gate dielectric barriers in vertical memory stacks.

Expanding sacrificial layers creates extension portions that prevent residual dielectric liners between the cell contact plug and gate electrodes.

Dicing-before-de-bonding scheme reduces warpage by maintaining wafer flatness during carrier removal for secure handling.

A display base plate uses wettability-matched radical groups and ligands to direct quantum dot self-assembly into precise sub-pixel patterns.

A hafnium oxide dielectric stack employs a seed layer to crystallize at low temperatures, resolving the trade-off between high capacitance and leakage current.

An opening in the protective film reduces residue generation during etching, preventing current leaks while maintaining high aperture ratio.

Direct metal etching with a patterned resin mask eliminates photolithography to lower fabrication costs while maintaining high light transmittance.

Differing transmittance and adhesion in adhering patterns enable precise LED rearrangement on temporary storage substrates, reducing manufacturing costs.

Dividing a single deep recess into two separate openings with controlled depths improves manufacturing precision while maintaining high element density.

A semiconductor memory device uses a sidewall spacer with varying thickness to protect internal components.

Segmented pin structures in a digital x-ray detector prevent line defects caused by particle contamination during manufacturing.

Dummy word lines in a hookup region replicate actual layers, enabling precise identification during failure analysis despite non-uniform polishing.

A semiconductor device uses a high-concentration latch-up suppression region to lower base resistance and prevent parasitic thyristor activation.

Atomic layer deposition creates conformal magnesium-doped zinc oxide films, resolving poor step coverage over complex substrate topographies.

Segmented light shielding films in CMOS image sensors reduce parasitic capacitance on gate electrodes, improving signal-to-noise ratio and operating speed.

Buried silicon pillars in through-holes form memory cells at electrode intersections, reducing lithography processes for higher storage capacity.

Pressurized air streams detach semiconductor layers from carriers, resolving edge ring adhesion without complex elastic mechanisms.