Connected Word Lines for Fast Memory Programming
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Solution Overview
Problem
Resistance-capacitance (RC) delays limit the speed of program and read operations in memory devices, and capacitance between word lines reduces performance, making it challenging to improve access speed and storage density simultaneously.
Innovation Solution
A group of word lines is driven with a common voltage signal during program and read operations, with options for permanent connection, switchable connection, or independent driving, allowing for high access speed and varying storage density configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If word lines are driven independently with separate voltage signals, then storage density can be maximized, but RC delays increase and access speed decreases
Solution Approach 1:
The memory device segments word lines into groups that can be independently controlled. Each group shares common word line connections to reduce RC delays, while still allowing independent addressing of individual memory cells within each group through selective activation of specific word line segments.
Solution Approach 2:
Multiple word lines are merged into shared common word line connections that serve multiple memory cell groups. This merging reduces the total number of independent voltage signal paths, thereby reducing RC delays and improving access speed while maintaining storage density through selective group activation.
2Quantity of substance
If more word lines are connected in parallel to increase storage density, then capacitance between word lines increases, but RC time constant increases and voltage ramp-up speed decreases
Solution Approach 1:
Word lines are segmented into multiple independent groups, each with its own dedicated voltage signal path and timing control. This segmentation allows voltage to ramp up faster in each group by limiting the capacitance that must be charged through each voltage path, while the overall storage density is maintained through parallel operation of multiple groups.
Solution Approach 2:
The system dynamically controls the activation and deactivation of different word line groups based on access patterns. By selectively activating only the necessary word line groups for each access operation, the effective capacitance is reduced, enabling faster voltage ramp-up while maintaining the capability for high storage density when all groups are utilized.
Data Source
AI summary
Apparatuses and techniques for fast programming and read operations for memory cells. A group of word lines comprising a selected word line and one or more adjacent word lines are driven with a common voltage signal during program and read operations. The word lines may be permanently connected to one another or connected by a switch. In another approach, the word lines are driven separately by common voltage signals. In a set of blocks, one block of memory cells can be provided with connected word lines to provide a relatively high access speed, while another block of memory cells has disconnected word lines to provide a higher storage density. In another aspect, the memory cells of a word line are divided into portions, and a portion which is closest to a row decoder is reserved for high access speed with a low storage density.