3D Semiconductor Memory Double Cross Point Array Fabrication
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Solution Overview
Problem
Existing three-dimensional semiconductor memory devices with cross-point array structures face challenges in increasing integration density and reducing fabrication complexity, particularly when stacking multiple memory layers, which leads to increased disturbance and decreased operation margin.
Innovation Solution
A method of fabricating semiconductor memory devices by forming two memory layers using a simplified process, where parallel conductive lines at different levels intersect to create memory cells, allowing for increased integration density and improved electric properties without the need for repeated selection device formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory layers are stacked vertically in existing cross-point array structures, then memory capacity increases, but disturbance between layers increases and operation margin decreases
Solution Approach 1:
The patent transitions from a planar two-dimensional cross-point array to a three-dimensional structure by stacking multiple memory layers vertically. Each layer contains conductive lines arranged in alternating directions, creating intersections that form memory cells in the third dimension, thereby increasing memory capacity while maintaining layer isolation to reduce disturbance.
Solution Approach 2:
The memory device is divided into multiple independent memory layers, where each layer contains a subset of conductive lines and memory cells. This segmentation allows independent formation and control of each layer, reducing the complexity and disturbance that would occur in a monolithic structure, while collectively achieving high memory capacity.
2Quantity of substance
If conventional cross-point array fabrication is used for multiple layers, then memory density increases, but fabrication complexity and process repetition increase
Solution Approach 1:
The patent employs a universal fabrication process that can form multiple memory layers simultaneously. The same patterning and deposition steps are applied repeatedly to create conductive lines in different orientations across multiple layers, eliminating the need for different fabrication approaches for each layer and significantly reducing overall fabrication complexity.
Solution Approach 2:
The fabrication process uses periodic repetition of patterning and deposition steps to form conductive lines in alternating directions across multiple layers. This periodic application of the same process sequence efficiently builds up the three-dimensional cross-point array structure, increasing memory density while maintaining process simplicity.
3Quantity of substance
If three conductive lines are required to form two memory layers at different levels, then memory layer formation is achieved, but at least two lines must be orthogonal which increases process complexity
Solution Approach 1:
Instead of requiring orthogonal arrangements within the same plane, the patent utilizes the vertical dimension to stack memory layers. Conductive lines in different layers can be parallel to each other, eliminating the need for complex orthogonal patterning processes while still achieving the required three-line intersection structure for memory cell formation.
Data Source
AI summary
Three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include first, second and third conductive lines disposed at different vertical levels to define two intersections, and two memory cells disposed at the two intersections, respectively. The first and second conductive lines may extend parallel to each other, and the third conductive line may extend to cross the first and second conductive lines. The first and second conductive lines can be alternatingly arranged along the length of third conductive line in vertical sectional view, and the third conductive line may be spaced vertically apart from the first and second conductive lines.