Ferroelectric Memory Device Weak Erase Operation
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Solution Overview
Problem
Current memory devices face challenges in efficiently storing data using ferroelectric layers due to issues with trapped electrons affecting the ferroelectricity and memory window stability, leading to unstable operation and characteristics.
Innovation Solution
The implementation of a ferroelectric memory device that includes a weak erase operation after the program sequence to remove trapped electrons, ensuring the polarization state corresponds to stored data and maintaining a desired memory window without waiting for natural emission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored using ferroelectric layer polarization characteristics, then non-volatile memory storage is achieved, but trapped electrons affect ferroelectricity and memory window stability causing unstable operation
Solution Approach 1:
A weak erase operation is performed before the read operation to remove trapped electrons that accumulate during the program operation. This preliminary action ensures that the ferroelectric layer is in a clean state without trapped electrons that would interfere with accurate reading, thus resolving the contradiction between maintaining stored data and eliminating harmful trapped electrons
Solution Approach 2:
The patent acknowledges that trapped electrons naturally accumulate during program operations but converts this harmful effect into a beneficial process by introducing a controlled weak erase operation. This operation selectively removes trapped electrons without affecting the stored polarization state, transforming the harmful trapped electron accumulation into a manageable and reversible process that enhances overall memory reliability
2Reliability
If natural emission of trapped electrons is waited for, then memory window stability is restored, but operation time is significantly extended
Solution Approach 1:
The patent replaces the passive natural emission process (thermal runaway mechanism) with an active controlled electrical process. Instead of waiting for trapped electrons to naturally emit through thermal effects, a controlled weak erase voltage is applied to actively remove trapped electrons through a controlled electrical field, substituting a slow natural physical process with a faster controllable electrical process
Solution Approach 2:
The patent changes the electrical parameters (voltage magnitude and pulse duration) of the weak erase operation to optimize the removal of trapped electrons. By carefully controlling the voltage parameters to be below the threshold that would affect stored data but sufficient to remove trapped electrons, the memory window stability is restored quickly without affecting the stored information, thus resolving the time-stability contradiction
3Reliability
If weak erase operation is implemented after program sequence, then trapped electrons are removed and memory window is stabilized, but additional operation steps are required
Solution Approach 1:
The patent merges the weak erase operation with the existing read operation sequence, where the weak erase is performed immediately before the read operation. This merging of functions reduces the overall operational complexity by combining two necessary steps (removing trapped electrons and reading data) into a single integrated operation sequence, thus resolving the contradiction between enhancing reliability and maintaining operational simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the operation and characteristics of the ferroelectric transistor by securing a desired memory window in a shorter time, improving the reliability and efficiency of data storage.
Implementation Method 1
a memory device that stores data by utilizing the polarization characteristics of a ferroelectric layer
Implementation Method 2
a third operation of applying a second voltage between the third conductive layer and the first pillar, wherein the first voltage has a first potential difference between the third conductive layer and the first pillar, a potential of the third conductor layer is lower than a potential of the first pillar, the second voltage has a second potential difference between the third conductive layer and the first pillar, the second potential difference is smaller than the first potential difference, a potential of the third conductor layer is lower than a potential of the first pillar
Data Source
AI summary
According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.