Non-Uniform Gate Spacers for Raised Source/Drain Capacitance Control
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Solution Overview
Problem
In advanced semiconductor-on-insulator technology platforms, the increased resistance of ultra-thin semiconductor layers necessitates raised source/drain regions for field effect transistors (FETs), which lead to a performance-degrading increase in overlap capacitance between the raised source/drain regions and the gate structure.
Innovation Solution
A semiconductor structure with a planar semiconductor-on-insulator FET featuring a thicker spacer at the top sidewall and a thinner spacer at the bottom sidewall, allowing for epitaxial silicon growth closer to the lower gate portion while maintaining a larger distance from the gate at the top, thereby reducing overlap capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If raised source/drain regions are formed to boost saturation current, then current drive capability is improved, but overlap capacitance increases degrading performance
Solution Approach 1:
The spacer structure transitions from uniform thickness to non-uniform thickness, with the top portion being thicker than the bottom portion. This local differentiation allows the bottom spacer to permit close source/drain proximity for high saturation current, while the top spacer provides extended separation to reduce overlap capacitance between the raised source/drain regions and the gate.
Solution Approach 2:
The invention addresses the lateral spacing problem by introducing a vertical dimension variation in the spacer structure. By making the spacer thickness non-uniform through the vertical dimension (thinner at bottom, thicker at top), the solution simultaneously achieves close lateral proximity at the source/drain-gate interface for current enhancement while maintaining lateral separation at the top for capacitance reduction.
2Productivity
If source/drain regions are positioned closer to enhance performance, then FET performance is improved, but overlap capacitance increases
Solution Approach 1:
The spacer structure transitions from uniform thickness to non-uniform thickness, with the top portion being thicker than the bottom portion. This local differentiation allows the bottom spacer to permit close source/drain proximity for high saturation current, while the top spacer provides extended separation to reduce overlap capacitance between the raised source/drain regions and the gate.
Solution Approach 2:
The invention addresses the lateral spacing problem by introducing a vertical dimension variation in the spacer structure. By making the spacer thickness non-uniform through the vertical dimension (thinner at bottom, thicker at top), the solution simultaneously achieves close lateral proximity at the source/drain-gate interface for current enhancement while maintaining lateral separation at the top for capacitance reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances FET performance by allowing closer proximity of source/drain regions at the bottom while minimizing overlap capacitance through the strategic use of spacers, thus optimizing performance without degrading it due to increased capacitance.
Implementation Method 1
the raised source/drain regions result in a corresponding performance-degrading increase in overlap capacitance (Coy) between the raised source/drain regions and the gate structure
Data Source
AI summary
Disclosed are a semiconductor structure and method of forming the structure. The structure has a semiconductor layer. A gate structure is located on the semiconductor layer. The gate structure has a sidewall spacer having a first section on the semiconductor layer and positioned laterally adjacent to the gate structure and further having a second section above and wider than the first section and positioned laterally adjacent the gate structure. A source/drain region is on the semiconductor layer and positioned laterally adjacent to the first section and the second section of the sidewall spacer.