Crosspoint Memory Electrode Deposition for Low-Roughness Contacts

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Solution Overview

Problem

Current deposition techniques for highly-resistive material layers in memory cells result in intrinsic roughness, leading to discontinuities in ohmic contact layers, high resistance, and potential cross-contamination between phase change and select device regions, affecting device performance and reliability.

Innovation Solution

Depositing highly-resistive material layers using vapor deposition techniques at low temperatures (between 20-40°C) with controlled substrate bias voltage to achieve smoother surfaces and reduce intrinsic roughness, thereby improving ohmic contact continuity and preventing cross-contamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional deposition techniques are used for highly-resistive material layers, then the deposition process is simpler and faster, but the layer exhibits high intrinsic roughness causing discontinuities in ohmic contact layers

Engineering Contradiction:

Improvesurface roughnessVSAvoiddeposition process complexity

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies parameter changes by modifying the deposition temperature to below 40°C and applying substrate bias voltage during the deposition process. These parameter changes transform the deposition conditions to achieve smoother highly-resistive material layers with intrinsic roughness less than 3% of layer thickness, resolving the contradiction between manufacturing precision and ease of manufacture

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent employs periodic action through alternating current (AC) bias voltage applied during deposition. This periodic voltage application creates oscillating electric fields that control material deposition dynamics, enabling smooth layer formation while maintaining deposition efficiency, thus addressing both surface roughness and process complexity

Inventive Principle:

Principle #19Periodic action

2Reliability

If conventional deposition is used, then the process is faster, but ohmic contact layers exhibit discontinuities and high resistance

Engineering Contradiction:

Improveohmic contact continuityVSAvoiddeposition speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

By changing the deposition temperature to below 40°C and applying substrate bias voltage, the patent achieves continuous ohmic contact layers with low resistance. The modified parameters ensure proper material flow and adhesion during deposition, maintaining reliability while managing deposition speed through optimized process conditions

Inventive Principle:

Principle #35Parameter changes

3Reliability

If conventional deposition techniques are used, then the deposition process is simpler, but cross-contamination occurs between phase change and select device regions

Engineering Contradiction:

Improveregion isolationVSAvoiddeposition process control

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses parameter changes in deposition temperature and substrate bias voltage to achieve precise material placement. These controlled parameters prevent material spread into adjacent regions, ensuring proper isolation between phase change and select device regions while maintaining manageable process control through monitored deposition conditions

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in lower intrinsic roughness (<3% of the layer's thickness), improved threshold voltage stability, reduced cross-contamination, and enhanced device performance with better etch fronts and reduced stack height, leading to improved structural yield and faster memory device operation.

Implementation Method 1

Depositing highly-resistive material layers using vapor deposition techniques at low temperatures (between 20-40°C)

Methodology Applied

Scientific EffectVapor deposition: Physical Vapour Deposition

Implementation Method 2

with controlled substrate bias voltage to achieve smoother surfaces and reduce intrinsic roughness

Methodology Applied

Scientific EffectSubstrate bias voltage control:

Data Source

PatentUS20230354723A1Structure and method of depositing memory cell electrode materials with low intrinsic roughness

Publication Date: 2023.11.02 INTEL CORP

AI summary

In one embodiment, a crosspoint memory device is manufactured by forming a material stack and patterning the material stack to form a plurality of memory cells of the cross point memory device. Forming the material stack includes depositing a select device (SD) region material comprising chalcogenide, depositing a layer comprising carbon on the SD region material at a temperature below 40° C., depositing an ohmic contact layer on the layer comprising carbon, and depositing a phase change material (PM) region material comprising chalcogenide on the ohmic contact layer.