Semiconductor Interconnect Structure for Harsh Media Reliability
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Solution Overview
Problem
Semiconductor devices used in harsh environments face reliability issues due to high resistance in interconnects and the need for modifications in standard CMOS processes to achieve reliable connections between polysilicon and monosilicon contacts.
Innovation Solution
A semiconductor device with a stoichiometric passivation layer and interconnects comprising a metal alloy and structured polycrystalline semiconductor material, which allows for reliable electrical connections without damaging the interconnects and conductive paths, even at high temperatures, and can be produced using standard CMOS facilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard CMOS interconnects (aluminum or copper) are used to connect polysilicon and monosilicon contacts, then the resistance is low, but the device cannot operate reliably in harsh environments
Solution Approach 1:
The patent changes the material parameter from standard aluminum/copper interconnects to tungsten-based materials, which have different physical and chemical properties that enable harsh environment operation while maintaining CMOS compatibility
Solution Approach 2:
The patent uses composite structures combining tungsten plugs with tungsten silicide layers to achieve both low resistance and reliability in harsh environments, leveraging the complementary properties of different materials
2Reliability
If platinum is used as interconnect material for harsh media applications, then reliability in harsh environments improves, but the resistance increases significantly
Solution Approach 1:
The patent combines tungsten (low resistance) with tungsten silicide (harsh environment stability) to create a composite interconnect structure that achieves both low resistance and reliability, avoiding the high resistance problem of pure platinum
3Ease of manufacture
If edge contact method is used to connect polysilicon and monosilicon, then connection is achieved, but standard CMOS processing must be modified and quality monitoring becomes complex
Solution Approach 1:
The patent introduces tungsten plugs as intermediary elements that facilitate the connection between polysilicon and monosilicon contacts, enabling standard CMOS processing without requiring complex edge contact techniques or dedicated quality monitoring modules
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides increased chemical and mechanical robustness, reduces leakage currents, and maintains low resistance, enabling reliable operation in harsh media while avoiding the need for dedicated process control modules for quality monitoring.
Implementation Method 1
a stoichiometric passivation layer which covers the first and second doped semiconductor layer and the oxide layer
Implementation Method 2
The interconnect is electrically connecting the first doped semiconductor layer with the second doped semiconductor layer
Implementation Method 3
an oxide layer covering the first doped semiconductor layer and the second doped semiconductor layer
Data Source
Figure 1~2
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AI summary
A semiconductor device (100) comprising a first and second doped semiconductor layer (112, 122), an oxide layer (127) covering the first and second layer (112, 122), and an interconnect and/or a conductive path (121); the interconnect which electrically connects the first and second layer (112, 122) comprises a metal alloy (124) which has a first part in contact with the first layer (112) and a second part in contact with the second layer (122), wherein a part of the metal alloy between the first and the second part crosses over a sidewall (133) of the second layer (122); the conductive path (121) comprises polycrystalline semiconductor material; at least one electronic component (115) is formed in the first and/or second layer (112, 122); the semiconductor device moreover comprises a stoichiometric passivation layer (128) which covers the first and second layer (112, 122) and the oxide layer (127).