Vertical NAND Memory Recess Segmentation for Density and Precision
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Solution Overview
Problem
Current memory devices face challenges in achieving high element density and small size while maintaining simplified manufacturing processes, particularly in the fabrication of vertical channel NAND flash memory devices, which require precise control over recess depths and widths to optimize performance and reduce unwanted resistance and current limitations.
Innovation Solution
The memory structure and manufacturing method involve forming two recesses with controlled depths and widths, where the second insulation recess has a larger width than the first, allowing for easier alignment and etching processes, and a channel layer is positioned on the sidewalls of the second recess, enabling better control over the channel layer's range and facilitating treatments like heat treatment to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single deep recess is formed in the memory structure, then the element density can be increased, but the manufacturing precision becomes difficult to control due to the large total depth
Solution Approach 1:
The single deep recess is divided into two separate recesses: a first recess extending from the top surface to a first depth, and a second recess extending from the bottom surface to a second depth. This segmentation allows each recess to be formed with controlled depth, improving manufacturing precision while maintaining the overall deep structure needed for high element density.
2Quantity of substance
If the recess width is reduced to increase element density, then the memory device size decreases, but the unwanted resistance and current limitations increase
Solution Approach 1:
The channel layer is selectively positioned only in the second recess (from the bottom surface) rather than uniformly throughout the entire structure. This local quality approach allows the channel layer to be concentrated where needed for optimal electrical performance, reducing unwanted resistance while maintaining high element density through the segmented recess structure.
3Reliability
If the channel layer is extended throughout the entire recess structure, then the current flow is improved, but the manufacturing complexity increases
Solution Approach 1:
The channel layer is extracted from the first recess and positioned only in the second recess. This extraction simplifies the manufacturing process by reducing the complexity of channel layer formation and patterning, while still achieving improved current flow through the strategic placement of the channel layer in the bottom portion of the structure.
Data Source
AI summary
A memory structure and a manufacturing method thereof are provided. The memory structure includes a bottom oxide layer, a first conductive layer on the bottom oxide layer, a first insulation recess, a plurality of insulating layers on the first conductive layer, a plurality of second conductive layers, a second insulation recess, a channel layer on a sidewall of the second insulation recess, and a memory layer located between the channel layer and the second conductive layers. The first insulation recess has a first width and penetrates through the first conductive layer. The second conductive layers and the insulating layers are interlacedly stacked, and the second conductive layers are electrically isolated from the first conductive layer. The second insulation recess located on the first insulation recess has a second width larger than the first width and penetrates through the insulating layers and the second conductive layers.