Recess-Filled Semiconductor Structures for CTE Mismatch Relief
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Solution Overview
Problem
Conventional semiconductor devices face issues with excess cost, inadequate integration, decreased reliability, and large dimensions due to stress and thermal expansion mismatch between dissimilar materials, particularly evident in Metal-Insulator-Metal (MIM) capacitor structures and heterojunction semiconductor materials like silicon carbide (SiC) on silicon substrates.
Innovation Solution
The implementation of a filled recessed structure with dissimilar materials in a patterned configuration, such as a honeycomb pattern, on a substrate to reduce thermal expansion coefficient (CTE) mismatch, where the fill material's CTE is intermediate between the substrate and the material being stacked, thereby reducing stress and improving integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dissimilar materials are stacked together in semiconductor devices, then integration and functionality are improved, but stress and thermal expansion mismatch cause delamination and cracking
Solution Approach 1:
The patent divides the structure into discrete recess regions separated by intervening substrate portions. This segmentation allows the fill material to be localized in specific areas where CTE mismatch compensation is needed, while the substrate remains intact in intervening regions, creating a modular approach to stress management.
Solution Approach 2:
The fill material acts as an intermediary substance placed within recesses of the substrate. This intermediate layer has a CTE that is intermediate between the substrate and the stacked structure, serving as a buffer that gradually transitions thermal expansion properties and reduces stress concentration at interfaces.
2Reliability
If alumina substrates are used for MIM capacitor structures, then CTE mismatch is reduced, but manufacturing cost increases
Solution Approach 1:
Instead of changing the entire substrate material from silicon to alumina, the patent applies the CTE-matching fill material locally only in specific recess regions where MIM capacitor structures will be formed. This localized approach provides the CTE benefits where needed while maintaining the cost advantage of using silicon substrates elsewhere.
Solution Approach 2:
The patent creates a composite structure by combining silicon substrate with fill material having intermediate CTE properties. This composite approach within the recess regions provides the thermal expansion characteristics similar to alumina substrates while maintaining the overall silicon substrate architecture for cost-effectiveness.
3Adaptability or versatility
If SiC structures are stacked on silicon substrates, then heterojunction performance is improved, but large CTE mismatch causes stress and reliability issues
Solution Approach 1:
The fill material serves as an intermediary layer between silicon substrates and SiC stacked structures. This intermediate material has CTE properties that are between silicon and SiC, creating a gradual transition that reduces the thermal expansion shock and mechanical stress at the SiC-silicon interface.
Solution Approach 2:
The recesses are pre-formed in the silicon substrate before stacking the SiC structures. This preliminary preparation creates ready-made cavities that will be filled with the CTE-matching material, establishing the stress-compensation architecture in advance before the heterojunction structures are introduced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the resistance to CTE mismatch, reducing delamination and cracking issues, and improves the performance and reliability of semiconductor devices by optimizing the stress and CTE mismatch between dissimilar materials, allowing for more cost-effective manufacturing on silicon substrates.
Implementation Method 1
reduce thermal expansion coefficient (CTE) mismatch
Data Source
AI summary
A semiconductor device includes a work piece comprising a first material, a first side, a second side opposite to the first side, and a first coefficient of thermal expansion (first CTE). Recesses extend into the work piece from the first side and includes a pattern. A second material having a second CTE is within the recesses and is over the first material between the recesses; and A third material having a third CTE is over one of the second side or the second material. The third CTE and the second CTE are different than the first CTE.