Offset Chip Stacking in Resin-Sealed Semiconductor Packaging
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices face challenges in improving throughput during the process of attaching substrates to sheets, fragmenting them into chips, and sealing these chips, as they require manual handling and are inefficient in terms of chip spacing and stacking.
Innovation Solution
A method involving the attachment of substrates to sheets, fragmentation into chips, expansion of the sheet to widen chip spacing, covering with resin to form sealed bodies, and stacking these bodies with offset chip positions to enhance compact mounting and stability, utilizing a semiconductor manufacturing apparatus with precise positioning and expansion mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If substrates are attached to sheets and fragmented into chips for sealing, then semiconductor devices can be manufactured, but the throughput is low due to manual handling and inefficient chip spacing
Solution Approach 1:
The substrate is fragmented into multiple individual chips through a dicing process, dividing a single large substrate into numerous smaller chip units that can be independently handled and mounted, thereby increasing manufacturing throughput while reducing manual handling requirements
Solution Approach 2:
The patent transitions from two-dimensional chip arrangement on a substrate to three-dimensional stacked bodies where multiple sealed bodies are vertically stacked with offset chip positions, enabling higher density mounting and improved throughput without increasing the footprint area
2Area of stationary object
If chips are mounted in traditional alignment, then mounting is straightforward, but space utilization is inefficient and stacking is unstable
Solution Approach 1:
The patent employs asymmetric offset positioning where chips in upper stacked bodies are positioned at different locations relative to chips in lower bodies, creating an interlocking configuration that improves stacking stability and optimizes space utilization by preventing direct vertical alignment
Solution Approach 2:
Multiple sealed bodies containing chips are nested vertically in stacked configurations, with each sealed body containing and protecting its chips while being integrated into a larger three-dimensional structure, enabling efficient space utilization and stable mounting
Data Source
AI summary
A method for manufacturing a semiconductor device is provided. The manufacturing method includes attaching a substrate to a sheet. The manufacturing method includes fragmenting the substrate into a plurality of individual chips. The manufacturing method includes expanding the sheet to widen the spacing between the plurality of chips. The manufacturing method includes covering the main surface and side surface of each of the plurality of chips with resin and sealing the chips to form a sealed body. The manufacturing method includes forming a stacked body in which a plurality of sealed bodies are stacked. The plurality of sealed bodies include a first sealed body and a second sealed body. Forming the stacked body includes stacking the second sealed body on the first sealed body in a state where the position of the chip in the second sealed body is offset in a direction in the plane with respect to the position of the chip in the first sealed body.