Dummy Word Lines for 3D NAND Failure Analysis
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Solution Overview
Problem
In nonvolatile semiconductor memory devices, particularly in 3D stacked NAND flash memory, performing failure analysis on word lines is challenging due to non-uniform polishing and difficulty in determining the layer of the exposed word line, which hinders accurate identification of the word line to analyze for failure.
Innovation Solution
The implementation of a bit-line hookup region with dummy word lines and patterns that are identical in structure to the actual word lines, allowing for easy identification of the layer during failure analysis by confirming the step structure formed during etching, and providing a controlled dishing effect during polishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If word line failure analysis is performed on 3D stacked memory, then manufacturing quality control is improved, but difficulty in identifying word line layer increases due to non-uniform polishing
Solution Approach 1:
The patent creates dummy word lines that are identical copies of actual word lines in structure, material composition, and stacking sequence. These dummy word lines are placed in a dedicated analysis region where they undergo the same polishing process as real word lines, thereby replicating the non-uniform polishing effects. This allows analysts to identify the layer position of exposed word lines by comparing with the known structure of dummy word lines, solving the identification difficulty while maintaining reliability improvement.
Solution Approach 2:
The dummy word lines serve as an intermediary reference system between the polishing process and the failure analysis measurement. By introducing this intermediate structure that experiences the same processing variations but has known initial characteristics, the patent enables accurate layer identification despite the non-uniform polishing that would otherwise make measurement difficult.
2Difficulty of detecting and measuring
If dummy word lines are added for failure analysis, then word line layer identification is improved, but device structure complexity increases
Solution Approach 1:
The patent segments the memory device into functional regions and dedicated analysis regions. The dummy word lines are confined to a specific analysis region separate from the active memory cell array, allowing the added structural complexity to be localized to a non-critical area. This segmentation enables failure analysis functionality without significantly impacting the overall device complexity or active memory capacity.
Solution Approach 2:
The patent adds the dummy word line structure in a spatial dimension separate from the active memory array, utilizing available space in the 3D stacked structure. By placing dummy word lines in a dedicated analysis region rather than interspersing them throughout the memory array, the patent minimizes the impact on device complexity while still providing the necessary reference structure for layer identification.
3Area of stationary object
If dummy word lines are placed in limited region, then space utilization is improved, but risk of interference with peripheral transistors increases
Solution Approach 1:
The patent applies local quality by creating a spatially differentiated structure where dummy word lines are placed only in specific analysis regions with appropriate spacing from peripheral transistors. The dummy word lines have the same local structure as real word lines but are positioned in locations optimized for analysis purposes, ensuring sufficient distance from active transistor regions to prevent electrical or physical interference while maximizing space utilization in available areas.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device comprises a memory cell array including a first selection gate, word lines and a second selection gate stacked above a semiconductor substrate, and a memory pillar disposed through the first selection gate, word lines and second selection gate, a hookup region disposed adjacent to the memory cell array region in a first direction, and a dummy region disposed outside the memory cell array region and the hookup region, the dummy region including dummy word lines, each provided at the same layer as the associated word line.