3D Stacked Memory Device Through-Hole Pillar Integration
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in increasing memory cell integration while maintaining cost-effectiveness, as methods like simple stacking increase lithography processes and costs, limiting the reduction of chip surface area per bit and storage capacity.
Innovation Solution
A nonvolatile semiconductor memory device with a collectively patterned three-dimensionally stacked memory structure, where through-holes are formed in a stacked body with alternately stacked electrode and insulating films, and silicon pillars are buried within these holes, allowing for memory transistors to be formed at intersections, reducing the number of lithography processes and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are three-dimensionally stacked to increase integration, then storage capacity increases, but the number of lithography processes increases and manufacturing cost increases
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking of memory cells. Multiple electrode films and insulating films are stacked in the vertical direction to form a stacked body, with through-holes penetrating through multiple layers. This dimensional change allows significantly higher storage capacity within the same chip area without proportionally increasing lithography complexity, as the stacking is achieved through vertical film deposition rather than additional lateral patterning steps.
2Quantity of substance
If simple stacking and patterning methods are used to increase integration, then storage capacity increases, but manufacturing cost increases due to increased lithography processes
Solution Approach 1:
The patent merges multiple functions into the through-hole structure: the through-hole serves as both the patterning template and the channel for forming memory cells. By forming through-holes that penetrate the entire stacked body and then depositing films on the through-hole walls, the patent combines the patterning step with the memory cell formation step, eliminating the need for separate lithography processes for each stacked layer and thereby reducing manufacturing costs.
Solution Approach 2:
The through-hole acts as an intermediary structure that enables the formation of three-dimensionally stacked memory cells without requiring complex lithography. The through-hole is formed first as a template, and then electrode films and insulating films are deposited on its inner walls. This intermediary approach allows vertical stacking to be achieved through deposition processes rather than repeated lithography patterning, significantly reducing manufacturing complexity and cost.
3Quantity of substance
If chip surface area per bit is reduced by stacking, then storage capacity increases, but cost reduction is limited compared to downsizing within chip plane
Solution Approach 1:
The patent achieves higher storage capacity by utilizing the vertical dimension through stacking, rather than continuing to downsize cells in the lateral plane. By forming multiple electrode films and insulating films in the vertical direction and creating through-holes that penetrate these stacked layers, the patent dramatically increases the number of memory cells per unit chip area. This vertical scaling approach provides a more cost-effective path to higher capacity compared to continued lateral downsizing, as it avoids the exponentially increasing lithography complexity associated with smaller feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient data storage and retrieval while excluding memory cells with operation errors, ensuring reliability and reducing manufacturing costs by increasing the aspect ratio of through-holes and the number of memory cells per unit surface area.
Implementation Method 1
The charge storage film is provided between the electrode films and the semiconductor pillar
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a stacked body, a through-hole, a semiconductor pillar, and a charge storage film. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in the through-hole. The charge storage film is provided between the electrode films and the semiconductor pillar. Memory cells are formed at each intersection between the electrode films and the semiconductor pillar. The control circuit writs a first value to at least some of the memory cells, performs an erasing operation of the first value from the memory cell written with the first value, reads data stored in the memory cell having undergone the erasing operation, and sets the memory cell to be unusable in a case that the first value is read from the memory cell.