3D Wafer-Level Optical Transformer Integration for Easier Alignment
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Solution Overview
Problem
Current high voltage transformers, particularly those using chip-level integration, face challenges in scalability, manufacturability, and efficiency due to the need for numerous alignment steps and complex bonding processes, which can lead to increased costs and reduced performance.
Innovation Solution
The implementation of wafer-level integration using 3D interconnect technology, wafer bonding, and wafer-level packaging for high voltage optical transformers, which simplifies the alignment and bonding of solid-state light sources and photovoltaic arrays, enabling better scalability and efficiency through active alignment and the use of reflective layers for enhanced light coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If chip-level integration is used for high voltage transformers, then device compactness is improved, but manufacturing complexity and alignment difficulty increase
Solution Approach 1:
The patent transitions from planar chip-level integration to three-dimensional wafer-level integration. By stacking multiple functional layers (light source layer, optical coupling layer, photodetector layer, high voltage output layer) vertically within a single wafer structure, the invention achieves compact device volume while maintaining manufacturing simplicity through standard wafer fabrication processes rather than complex chip-level assembly and alignment operations
2Reliability
If chip-level integration with multiple alignment steps is used, then device functionality is achieved, but manufacturing time and cost increase
Solution Approach 1:
The patent merges multiple discrete chip-level components and alignment steps into a single integrated wafer-level structure. All functional elements (light sources, optical coupling media, photodetectors, and high voltage output terminals) are fabricated and assembled within one wafer using standard semiconductor processing techniques, eliminating the need for repeated alignment and bonding operations that would otherwise be required for chip-level integration
Solution Approach 2:
The patent performs preliminary fabrication of all functional layers and interconnections within the wafer structure before final device completion. By pre-integrating the light source layer, optical coupling layer, and photodetector layer with their respective interconnections during wafer fabrication, the invention eliminates subsequent alignment and assembly steps, thereby reducing manufacturing time and improving productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in more efficient and scalable high voltage optical transformers with reduced manufacturing complexity, improved light coupling, and enhanced performance, suitable for applications in compact devices such as wearable systems and medical devices.
Implementation Method 1
bonding a photovoltaic (PV) wafer to a second side of the carrier wafer opposite to the first side, where the photovoltaic wafer includes an active area and a conductive area located outside of the active area that is in electrical contact with the conductive layer
Implementation Method 2
bonding a photovoltaic (PV) wafer to a second side of the carrier wafer opposite to the first side, where the photovoltaic wafer includes an active area
Data Source
AI summary
A method of forming a high voltage optical transformer includes forming a via through a transparent carrier wafer, forming a conductive layer within the via, bonding a solid state lighting (SSL) package to a first side of the carrier wafer, and bonding a photovoltaic (PV) wafer to a second side of the carrier wafer opposite to the first side. The photovoltaic wafer may include an active area and a conductive area located outside of the active area that is in electrical contact with the conductive layer. The method further includes forming both an SSL contact with the solid state lighting package and a PV contact with the conductive layer on the same side of the carrier wafer.