3D Semiconductor Memory Stack for Higher Density Erase Control
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration density and cost due to the need for high-cost equipment for fine pattern formation, which restricts their performance and efficiency.
Innovation Solution
The development of three-dimensional semiconductor memory devices with vertically stacked gate electrodes and source conductive patterns, allowing for increased integration density and improved data storage patterns that optimize the gate induced drain leakage current during erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices use fine pattern formation techniques to increase integration density, then integration density is improved, but manufacturing cost increases due to high-cost equipment requirements
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple gate electrodes are stacked in the vertical direction (first direction perpendicular to substrate), creating a three-dimensional structure that increases storage capacity per unit area without requiring finer lateral patterning, thereby avoiding the need for high-cost fine pattern formation equipment
Solution Approach 2:
The memory device is segmented into multiple independent gate electrodes stacked vertically, with each gate electrode forming part of a separate memory cell. This segmentation allows each cell to be independently controlled and formed using standard patterning processes, reducing manufacturing complexity and cost while achieving high integration density through vertical stacking
2Quantity of substance
If three-dimensional memory cells are constructed with vertically stacked gate electrodes, then integration density is improved, but device complexity increases
Solution Approach 1:
The vertically stacked gate electrodes serve multiple functions: each gate electrode acts as a control electrode for its corresponding memory cell, and collectively they form a compact three-dimensional array that achieves high integration density. The uniform vertical stacking pattern provides a scalable template that simplifies manufacturing while enabling complex functionality through the multi-layer structure
Data Source
AI summary
A three-dimensional semiconductor memory device includes a substrate, an electrode structure including a plurality of gate electrodes sequentially stacked on the substrate in a first direction that extends perpendicular to an upper surface of the substrate, a source conductive pattern between the substrate and the electrode structure, a vertical semiconductor pattern penetrating the electrode structure and the source conductive pattern, and a data storage pattern extending in the first direction between the vertical semiconductor pattern and the electrode structure. A lower surface of the data storage pattern contacts the source conductive pattern. A portion of the lower surface of the data storage pattern is at a different height from the upper surface of the substrate, in relation to a height of another portion of the lower surface of the data storage pattern from the upper surface of the substrate.