Solid-State Devices TRIZ Cases

Multiple ESD diode arrangements and TSV wiring let 3D-IC I/O cells balance ESD protection, drive strength, power use, and manufacturing cost.

Coupling gratings in a waveguide split and redirect 3D image beams to align eye focus with binocular convergence, reducing dizziness.

Conductive posts and a common strip simplify high-density LED bonding, improving alignment flexibility, yield, and display brightness.

Micro pixel controllers placed between pixels cut display thickness and power use while preserving brightness control in inorganic LED modules.

An insulating passivation pattern isolates closely spaced micro-LED contact electrodes to cut contact defects and improve durability and light output.

Lens imaging modules placed between pixel units preserve camera function while removing forehead and chin areas for borderless full-screen display.

A grooved substrate and support-layer cavity shift metal wiring toward the neutral layer, reducing bend stress and breakage in narrow-bezel panels.

Selective carbon implantation grows a thicker gate silicide than source and drain silicides, cutting FET gate resistance without added area or process burden.

Selective group biasing and readout simplify avalanche photodiode wiring, cut crosstalk and noise, and improve reflected-light detection accuracy.

An encapsulation layer shields the first electrode-pad connection during conductive layer patterning, improving Micro-LED display reliability.

A staircase word-line layout with switches and contacts enables uniform, independent voltage control in stacked 3D NAND arrays.

A 2D metasurface routes multiple polarizations to adjacent pixels in one exposure, improving quantum efficiency without bulky rotating polarizers.

Wavelength-specific fine structures split and focus light onto matching pixels, improving image sensor color sensing without filter absorption loss.

A patterned glass support with narrow etched openings helps foldable displays resist cracks and creases without sacrificing foldability.

Adjacent electrodes create electric fields only in pathway areas, aligning light emitters while avoiding open-area misalignment and extra process cost.

Direct scintillator formation on the circuit layer cuts interlayers and bubbles, improving detection panel resolution, quantum efficiency, and durability.

An offset connecting region and elastic layer let stretchable display units deform more uniformly while preserving conductivity and light output.

A convex pixel lens, side-mirror anode, and UV shielding layer improve light extraction, widen viewing angle, and protect OLED emitters.

Thin barrier regions and a stepped gate suppress charge buildup and block leakage paths, improving e-mode HEMT gate reliability.

Precisely positioned radiation converters keep sub-pixel colors separate, improving wavelength control, color purity, and fine-pitch display resolution.

Independent biasing of paired gate electrodes lowers RRAM access voltage while preserving drive current for transistor scaling.

Segmented dielectric insulation with a capping layer helps dense memory cells limit leakage current, avoid shorts, and improve reliability.

Independently biased field plates and depletion transistors flatten the gate-drain field, reducing leakage and off-state stress.

A stacked LED layout places red emitters as separate top chips and uses insulated vertical connections to avoid contamination, shorts, and efficiency loss.

Varying pixel density and light transmittance across display regions enables under-screen cameras while reducing visible region boundaries.

Curved moth-eye recesses cut image sensor reflection while preventing insulation film and color filter peeling that adds noise and lowers yield.

Individual hemispherical lenses and fillet segments let LED arrays pack densely while improving light transmission and die protection.

Inclined refractive index layers redirect display light by total reflection and refraction to cut multilayer loss and extend the emission region.

A capped Bragg reflector cuts thickness and blocks moisture ingress in blue LED mesas, improving humidity reliability and chip bonding.

Interface doping in a trench Ge-Si optical sensor passivates defects, blocks electron leakage, and lowers dark current.

A reflective auxiliary electrode on the bank slope redirects trapped light while improving current spreading and color consistency in 3D QLED pixels.

A capacitor-layer tip structure channels and releases static electricity during film removal, preventing pixel damage and white spot defects.

Gradient hole-transport and emission-layer thicknesses improve OLED light uniformity, expand effective emitting area, and cut current loss.

Direct wafer bonding hermetically seals resin lenses in endoscope image pickup modules, improving moisture resistance without added films.

Barrier units surrounding display-panel electrical connections block moisture and oxygen, reducing ion migration, corrosion, and resistance drift.

An acute-angled TFT source region enables denser transistor layout for higher display resolution while preserving electrical characteristics.

Blue-first UV curing in an OLED color filter stack boosts adhesion, cuts cracking risk, and helps replace polarizers with a thinner, brighter panel.

A conductive film and floating guard region suppress X-ray-induced interface charge, reducing dark current and stabilizing capacitance.

An oxygen-absorbing metal layer near the IGZO channel captures non-bonded oxygen to stabilize threshold voltage and switching behavior.

Selective excavation of the auxiliary film layer over the opening area boosts visible-light transmittance while preserving TFT driving capability.

Selective activation of dual buffer-die interfaces boosts HBM bandwidth without increasing memory controller chip area.

A lateral-vertical Sziklai Darlington selector drives PCM and ReRAM cells at high voltage and current while shrinking unit cell footprint.

A roughened curved transparent resin extends resin interface distance between leads, improving dielectric strength in optical semiconductor modules.

Variable-width partition walls with protruding pillars prevent deformation, preserve luminance, and support misaligned emitters.

By integrating the OLED anode with the drain electrode, this case removes contact holes and cuts mask steps, cost, and parasitic capacitance.

A darkening layer on metal mesh wiring cuts electrode visibility while preserving solder attachment and lowering resistance in transparent LED displays.

FD-SOI isolation and an outer insulating layer curb buried word line coupling and disturbance in dense BCAT structures while improving uniformity.

A bilayer-doped GaN mesa enables selective electrochemical porosification across large substrates, reducing edge-center variation in micro-LEDs.

Deposited insulation around etched ground-plane regions replaces STI, cutting 3D circuit process cost and preserving thermal budget.

Auxiliary circuit routing across solder mask windows preserves bonding pad detection and reduces cold solder joints in mini LED backlights.

Oblique silicon pixel interfaces create total internal reflection, extending near-infrared absorption and reducing image artifacts.

Using molybdenum as the bottom electrode suppresses oxygen vacancies in ferroelectric memory, improving uniformity, yield, and wakeup-free reads.

A tuned UV absorber and initiator ratio improves resin curing, preserves surface hydrophilicity, and prevents residual films that disrupt ink spread.

A light-shielding layer doubles as a signal line to simplify optical sensing layout, raise configuration density, and improve sensing performance.

Inorganic nanorod pixels cut visible-light loss and crosstalk in sub-1 μm image sensors while improving thermal reliability and photoelectric conversion.

Hot carrier injection lowers access transistor threshold voltage in weak MRAM cells, cutting bit errors and improving array yield.

A bottom conductive layer fully covers the drain electrode to enlarge contact area, cut resistance, and lower display power use.

Graphene carbon electrodes in vertical OLED transistors cut source-drain voltage while improving brightness, efficiency, and AMOLED stability.

A temperature-responsive barium titanate resistance path limits SiC overcurrent density, delaying thermal destruction during short-circuit stress.

Exciplex formation between two organic complexes helps OLEDs deliver stable green and red emission with high efficiency and long operating life.

An asymmetric subpixel layout packs OLED pixels more tightly to raise resolution while easing fine metal mask limits and smoothing brightness distribution.

Prestructured metal carrier sections replace warping lead-frame bars, enabling stable singulation, lower thermal resistance, and driver chip shielding.

Varying inductor track widths across parallel windings raises Q-factor and lowers TCL in CMOS LC oscillators over broad temperatures.

Vertical gate stacking and shaped data storage layers raise memory density while improving erase behavior and lowering fine-patterning cost.

A multilayer sub-electrode layout helps a foldable digitizer withstand stress at two folding axes while maintaining touch functionality.

A thermally formed metal-oxide buffer layer eases expansion mismatch at the electrode interface, cutting leakage current and improving dielectric capacitance.

Angled sidewalls and horizontal gate surfaces expand effective channel width, boosting FET speed and signal-to-noise ratio.

An inverse-taper spacer redistributes folding stress in flexible OLED stacks to improve adhesion, reduce peeling, and limit current leakage.

Fluorine plasma treatment of the ZnO electron transport layer cuts defects, improves charge transport, and extends QDLED half-life.

Convex and concave edge regions trap dislocation defects in dummy areas, reducing pixel leakage in dense BSI image sensors.

Shared gate and electrode layers let oxide and polysilicon transistors use fewer mask steps, lowering LTPO substrate cost while preserving aperture ratio.

Using TMDs or proximitized graphene, this MESO readout boosts spin-to-charge voltage and supports PMA magnets for scalable cascading.

A chemically inert liner around light guides blocks corrosive reaction solutions from reaching circuitry while preserving compact optical detection.

A dual-gauge lead frame helps current sensor ICs meet creepage and isolation requirements for high-voltage, high-current sensing.

Selective etching creates voids between conductive tiers in 3D memory cell strings, reducing shorting while preserving upper select-gate insulation.

Recessed and protruding display electrodes create extra placement space for light emitting elements, raising pixel density and luminance per area.

A dual-source conductive stack and vertical channels raise 3D memory density while protecting peripheral transistors during thermal processing.

An insulating pattern, separated contact electrodes, and a void structure help rod-type LEDs avoid shorts and contact defects in displays.

Openings placed in sparse DRAM capacitor regions remove sacrificial oxide without damaging bottom electrodes, preserving storage capacitance.

A floating-layer diode with control gate cuts freewheeling diode VF and recovery loss in RC-IGBTs without lifetime killers.

A diffusion barrier layer blocks electrode species during high-temperature baking, preserving PMC switching, endurance, and breakdown voltage.

A self-aligned metal and trench isolation grid avoids dry-etch silicon damage in BSI image sensors, improving optical isolation and sensitivity.

A dense low-hydrogen IGZO interfacial layer suppresses hydrogen loss and oxygen deficiency, improving stacked imaging element reliability.

An interposer-in-board package improves heat dissipation in large-area semiconductor X-ray detectors while supporting dense pixel arrays.

Self-aligned phosphor cavities and light-blocking metal cut optical crosstalk in dense micro-LED arrays while avoiding die-to-die alignment.

Segmented spacers held by bumps and trenches resist external pressure, maintain the cell gap, and reduce display light leakage.

A 3D outer cover layer shields thin OLED signal links during etching while reducing RC delay to support high-resolution image quality.

Surface plasmon polaritons boost sub-wavelength photodetector response by enabling tunneling-based photocurrent and higher quantum efficiency.

A hyperbolic metamaterial coupled to the quantum well boosts radiative recombination and light extraction in small LED pixels.

Patterned semiconductor polarizers and a reflective grid improve backside image sensor sensitivity by filtering unwanted light and reducing pixel interference.

Integrated RGB iLED pixels use shared series or parallel driving to simplify wiring, improve white-light efficiency, and support higher display resolution.

A shared electrode and TFT layer layout combines touch control with light sensing while reducing light loss, interference, and Moire patterns.

Matching the ROIC substrate CTE to the detector substrate removes thermal expansion strain, improving interconnect reliability and reducing bowing.

Varying pillar diameter and insulator thickness suppresses charge breakthrough, improving data retention in stacked semiconductor memory.

Pressure differences in a through-hole substrate vertically align and secure light emitting elements, improving light output and placement accuracy.

A phase-transition material layer modulates free-layer anisotropy in MRAM, lowering switching current while preserving thermal stability.

Series-connected micro LED sub-pixels split red emission by gray range to improve low-luminance color uniformity and power use.

Activating diced chips before sheet stretching keeps bonding surfaces clean, improving bond strength and reducing chip-to-substrate defects.

Reflective grid walls around wavelength-converting pixels cut micro-LED crosstalk while simplifying dense array fabrication.

A crystalline switching layer uses line defects to guide metal ion migration and form conductive filaments between electrodes.

Segmenting the LED array into isolated sub-regions improves heat dissipation efficiency while maintaining high luminance output for larger LCD panels.

A ring dummy pattern guides contact hole formation through layered insulating structures to ensure accurate electrode connection.

Tapered electrode structures localize conductive filaments within solid electrolyte openings to reduce feature sizes below lithographic limits.

A transistor uses a fly-over conductor to apply bias voltage offsetting trapped charge effects in insulating materials.

Multiple photo processes and width control spacers create 30 nm openings in insulation layers, resolving resolution limits that cause defects.

A masking layer protects the image sensor area while an optical resonator filters light frequencies to increase sensitivity.

A supporting substrate prevents bending of thin glass substrates during manufacturing, enabling precise assembly without permanent structural modifications.

Insetting LED chips into a transparent ceramic submount reduces thermal resistance and boosts brightness by optimizing heat dissipation paths.

A light emitting device uses a wider insulating separation region to arrange underfill material without covering the semiconductor element side surfaces.

Nested protection layers with specific overlap distances prevent vapor intrusion, extending OLED display panel service life.

Integrating detection elements on a single flexible board reduces assembly time and wiring errors compared to individual boards.

Vertical charge holding parts in CMOS image sensors prevent optical noise and preserve aperture ratio.

A reverse memory cell uses a charge-trapping layer to exchange electric charge via tunneling through dielectric layers.

Fixing a wafer on an ice layer prevents internal stress from resin application, preserving the wafer's natural shape during protective member formation.

Stacked infrared photodetector layers use a dedicated skimming electrode to divert dark current electrons away from the primary signal path.

Replacing multiple spacer layers with one conformal silicon nitride gap filling layer reduces chip area occupancy in 1.5T SONOS memory fabrication.

Independent ring-shaped packaging units increase bonding area to offset room temperature bonding defects, reducing fracture probability in OLED displays.

Reflowing solder into substrate openings fills gaps and prevents gas-trapped voids that cause cracking during heat treatment.

Multi-layered package embeds side wall barriers within flexible substrates to block moisture and oxygen ingress.

A LOCOS isolation structure uses a CVD oxide film on the high voltage region to relax electric field intensity.

A surface layer formed through a Diels-Alder addition reaction on polyaromatic organic semiconductors enhances electronic properties and stability.

A thermally tunable optical waveguide uses a structural gap to isolate the heater from the substrate, reducing thermal coupling.

Bonding a flexible film to a planarized substrate region connects peripheral wiring, preventing cracks when bending the display bezel.

A signal processing circuit uses oxide semiconductor memory cells to retain data without continuous power.

Vertical channel transistors overcome horizontal channel limitations by using dimensionality change to boost integration density and current driving capability.

A rotatable supporter bends a display substrate's outer region to minimize bezel width while maintaining structural integrity.

Laser ablation patterns intersecting inductive and drive electrodes within a single cathode layer to simplify manufacturing steps.

A concave substrate structure positions heat-conducting adhesive layers beneath LED chips to manage thermal output.

Curving the OLED light-emitting unit increases the emission area and view angle to counter narrow viewing cones from microcavity interference.

A MEMS device integrates a CMOS substrate with conductive features on the back surface to establish electrical connections through metallization layers.

A parallel storage capacitor shares a thin film transistor electrode through single patterning to boost capacitance.