3D Semiconductor Memory Source Stack for Dense Reliable Cell Arrays
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration density due to expensive equipment required for fine pattern formation, necessitating the development of three-dimensional semiconductor memory devices with enhanced electrical and reliability characteristics.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a substrate, peripheral circuit structure, and cell array structure, featuring alternating interlayer insulating layers and conductive patterns, including gate electrodes, source conductive patterns, and vertical channel structures made of semiconductor materials, which increase integration density and prevent peripheral transistor damage during thermal processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional semiconductor devices are used to achieve fine pattern formation, then manufacturing precision can be improved, but integration density is limited due to expensive equipment requirements and area constraints
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked in the vertical direction, with each layer containing memory cells formed by alternating conductive patterns and insulating layers. This dimensional change enables significantly higher integration density without requiring proportionally more expensive fine pattern formation equipment, as the stacking approach leverages existing planar fabrication capabilities extended into the vertical dimension.
2Productivity
If three-dimensional stacked structures are implemented to increase integration density, then productivity is improved, but thermal processes may damage peripheral transistors located near the cell array
Solution Approach 1:
The patent divides the semiconductor device into distinct regions: a cell array region containing the stacked memory cells and a peripheral circuit region containing control transistors. Physical separation and spatial segmentation allow thermal processes applied to the cell array region to be isolated from peripheral transistors, preventing thermal damage while maintaining high integration density in the stacked structure.
Solution Approach 2:
The patent introduces an interlayer insulating layer as an intermediary between the stacked memory cell structure and peripheral circuits. This insulating layer acts as a thermal barrier and electrical isolator, protecting peripheral transistors from thermal damage during cell array processing while maintaining electrical connectivity where needed. The interlayer insulating layer mediates between the high-density cell array and the sensitive peripheral circuits.
3Productivity
If multiple conductive patterns are stacked to form three-dimensional memory cells, then integration density is improved, but device complexity increases due to multiple materials and fabrication steps
Solution Approach 1:
The patent employs a repeating unit structure where alternating conductive patterns and insulating layers serve multiple functions simultaneously. The conductive patterns function as both word lines and source/drain regions depending on their position and connectivity, while insulating layers provide both electrical isolation and structural support. This multi-functionality reduces the number of distinct fabrication steps required compared to traditional approaches that would require separate structures for each function.
Solution Approach 2:
The patent merges the formation of multiple conductive patterns and insulating layers into a single integrated stacking process. Rather than forming each layer separately through distinct fabrication sequences, the method combines these elements into unified formation steps where conductive patterns and insulating layers are alternately deposited and patterned together. This merging approach simplifies the overall fabrication process while achieving high integration density through the vertical stack.
Data Source
AI summary
A three-dimensional semiconductor memory device includes a substrate, a peripheral circuit structure provided on the substrate, and a cell array structure provided on the peripheral circuit structure. The cell array structure includes a stack including alternating interlayer insulating layers and conductive patterns, the conductive patterns including gate electrodes and a first source conductive pattern that is an uppermost pattern of the conductive patterns, a second source conductive pattern provided on the stack and in contact with a top surface of the first source conductive pattern, the second source conductive pattern including a material different from a material of the first source conductive pattern, and vertical channel structures provided to penetrate the stack and to be inserted into a lower portion of the second source conductive pattern. The vertical channel structures include vertical semiconductor patterns connected to the second source conductive pattern.