Reverse Memory Cell Single Polarity Operation
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Solution Overview
Problem
Memory devices with gate-injected charge-storage layers are complex and limited by requiring both positive and negative voltages for programming and erasing, leading to increased design and process complexities, and are not suitable for 3-dimensional memory arrays due to low cell current and high mobility constraints.
Innovation Solution
A thin-film memory cell design with a charge-trapping layer and dielectric layers of different thicknesses allows for electric charge exchange between a conductive layer and the charge-trapping layer using a single polarity voltage, enabling programming, erasing, and read operations without the need for reversed polarity voltages, and can be used as a building block for 3-dimensional memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-channel memory cell is used with self-boosting technique, then program-inhibit operation is achieved, but device complexity increases and cell current decreases
Solution Approach 1:
The patent inverts the conventional memory cell structure by using n-channel transistors instead of p-channel, and reverses the polarity of voltages applied to source and drain. This inversion allows the memory cell to achieve program-inhibit operation without requiring the complex self-boosting technique, thereby reducing device complexity while maintaining reliability
Solution Approach 2:
The patent changes the electrical parameters of the memory cell by switching from p-channel to n-channel transistors and adjusting voltage polarities. This parameter change enables the memory cell to operate with simpler circuitry and achieve better cell current characteristics while maintaining the program-inhibit function
2Ease of operation
If both positive and negative voltages are applied for programming and erasing, then memory operations are achieved, but design complexity and process complexity increase
Solution Approach 1:
The patent makes the memory cell universal by enabling both programming and erasing operations to be performed using the same polarity of voltages. The n-channel memory cell structure allows flexible voltage application where both positive and negative voltages can be used for either programming or erasing, eliminating the need for separate circuit paths and reducing design complexity
Solution Approach 2:
By inverting the conventional voltage polarity scheme, the patent allows memory operations to be performed with simplified voltage requirements. The reversed polarity approach enables single-polarity operation modes that reduce the need for complex voltage generation and management circuits
3Productivity
If channel-injected charge memory cell structure is used, then high cell current is achieved, but 3-dimensional array implementation is not possible
Solution Approach 1:
The patent transitions from planar 2D memory cell structures to vertically stacked 3D configurations. By stacking multiple n-channel memory cells vertically and connecting them through shared source and drain regions, the invention achieves high cell current performance while enabling 3-dimensional memory array implementation
Solution Approach 2:
The patent combines multiple memory cells into a unified 3D structure by merging their source and drain regions. This consolidation allows shared electrical connections between stacked cells, maintaining high cell current characteristics while achieving compact 3D array architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution simplifies the design and power management of memory devices by allowing operations with a single polarity voltage, enhancing endurance and reducing complexity, while enabling the use of these cells in 3D arrays with improved cell current efficiency.
Implementation Method 1
when a sufficiently large potential difference is imposed between the conductive layer and the third deposited semiconductor layer, electric charge is exchanged between the conductive layer and the charge-trapping layer by tunneling through the second dielectric layer
Data Source
AI summary
A non-volatile “reverse memory cell” suitable for use as a building block for a 3-dimensional memory array includes a charge-trapping layer which is programmed or charged through gate-injection, rather than channel-injection. Such a reverse cell may be implemented as either an n-channel memory cell or a p-channel memory cell, without incurring design or process penalties, or any complexity in programming or erase operations. Furthermore, all reading, programming, erase, program-inhibiting operations may be carried out in the reverse memory cell using only positive or only negative voltages, thereby simplifying both the design and the power management operations.